Differences Among Altera® SoC Device Families

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ID 683648
Date 8/29/2025
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Document Table of Contents x
Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families x
Overview of HPS Modules HPS Micro Processor Unit Subsystem Differences Booting and Configuration Differences Cache Coherency Unit Differences Generic Interrupt Controller Differences HPS System Memory Management Unit Differences HPS On-Chip RAM Differences HPS Error Correction Differences HPS DMA Controller Differences HPS Clock Manager Differences HPS Reset Manager Differences HPS FPGA Manager Differences HPS System Manager Differences HPS Scan Manager Differences HPS Security Feature Differences HPS System Interconnect and Firewalls Differences HPS-FPGA Bridge Differences HPS General Purpose I/O Interface Differences I/O Pin Multiplexing Differences HPS Mailbox Differences HPS SDRAM Controller Subsystem Differences HPS NAND Flash Controller Differences HPS SD/eMMC Host Controller Differences Combo DLL PHY Differences HPS Quad SPI Flash Controller Differences HPS USB 2.0 OTG Controller Differences HPS USB 3.1 Gen1 Controller Differences HPS EMAC Differences HPS SPI Controller Differences HPS I2C Controller Differences I3C Controller Differences HPS UART Controller Differences HPS CAN Controller Differences HPS Timer Differences HPS Watchdog Timer Differences HPS CoreSight Debug and Trace Differences Revision History for Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families

HPS-FPGA Bridge Differences

HPS-FPGA Bridge Feature Cyclone® V SoC, Arria® V SoC Arria® 10 SoC Stratix® 10 SoC

Agilex™ 7

F-Series/I-Series/

M-Series SoC

Agilex™ 5

E-Series/D-Series SoC,

Agilex™ 3

C-Series SoC
HPS-to-FPGA (H2F) 32-, 64-, or 128-bit 32-, 64-, or 128-bit 32-, 64-, or 128-bit 32-, 64-, or 128-bit 32-, 64-, or 128-bit
Lightweight HPS-to-FPGA (LWH2F) 32-bit 32-bit 32-bit 32-bit 32-bit
FPGA-to-HPS (F2H) 32-, 64-, or 128-bit 32-, 64-, or 128-bit 128-bit
  • F-Series/I-Series: Single port 128-, 256-, or 512-bit
  • M-Series: Single port 128-, or 256-bit
 256-bit
F2SDRAM 32-, 64-, or 128-bit 32-, 64-, or 128-bit 32-, 64-, or 128-bit 64-, 128-, or 256-bit
Protocol Support AMBA AXI-3 AMBA AXI-3 AMBA AXI-4 + AMBA4 ACE-Lite AMBA 4 AXI4 + AMBA 4 ACE-Lite AMBA 4 AXI4 + AMBA 5 ACE5-Lite 19
Ready latency support for improved timing No Yes Yes Yes Yes

Although the HPS and the FPGA logic can operate independently, they are tightly coupled through a high bandwidth system interconnect built from high-performance ARM® Advanced Microcontroller Bus Architecture (AMBA® ) Advanced eXtensible Interface (AXI™) bus bridges.

Bus masters on soft logic cores in the FPGA fabric have access to HPS bus slaves through the FPGA-to-HPS bridge. Similarly, HPS bus masters have access to bus slaves in the FPGA through the HPS-to-FPGA bridge.

On Cyclone V, Arria V, and Arria 10 devices, the bridges are AMBA AXI-3 compliant and support simultaneous read and write transactions. Up to three masters in the FPGA fabric can share the HPS SDRAM controller with the processor.

On Stratix 10 devices, the FPGA-to-HPS bridge implements the AXI Coherency Extension (ACE) protocol, and passes through the CCU block.

The processor can be used to configure the core fabric under program control through a dedicated 32-bit configuration port.

19 You can use the Altera ACE5-Lite Cache Coherency Translator IP to connect any AXI or Avalon® memory-mapped interface FPGA Manager in the fabric to the F2H bridge. For more information about this IP, refer to the Embedded Peripherals IP User Guide.
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