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Overview of HPS Modules
HPS MPU Subsystem Differences
Stratix 10 HPS Interface to SDM
Booting and Configuration Differences
HPS Cache Coherency Controller Differences
HPS System Memory Management Differences
HPS On-Chip RAM Differences
HPS Error Correction Differences
HPS DMA Controller Differences
HPS Clock Manager Differences
HPS Reset Manager Differences
HPS FPGA Manager Differences
HPS System Manager Differences
HPS Scan Manager Differences
HPS Security Feature Differences
HPS Interconnect Differences
HPS-FPGA Bridge Differences
HPS General Purpose I/O Interface Differences
HPS I/O Configuration Differences
HPS SDRAM Controller Subsystem Differences
HPS NAND Flash Controller Differences
HPS SD/MMC Controller Differences
HPS Quad SPI Flash Controller Differences
HPS USB 2.0 OTG Controller Differences
HPS EMAC Differences
HPS SPI Controller Differences
HPS I2C Controller Differences
HPS UART Controller Differences
HPS CAN Controller Differences
HPS Timer Differences
HPS Watchdog Timer Differences
HPS CoreSight Debug and Trace Differences
Document Revision History
Visible to Intel only — GUID: cru1463082700603
Ixiasoft
HPS Interconnect Differences
| Interconnect Feature | Cyclone V SoC | Arria V SoC | Arria 10 SoC | Stratix 10 SoC |
|---|---|---|---|---|
| Interconnect Implementation | ARM® CoreLink™ Network Interconnect (NIC-301) | ARM® CoreLink™ Network Interconnect (NIC-301) | Arteris FlexNOC™ Network-on-Chip Interconnect | Arteris FlexNOC™ Network-on-Chip Interconnect |
| Firewall and Security Support | No | No | Yes | Yes |
| SDRAM scheduling implementation | Multi-port front end (MPFE) in hard memory controller (HMC) | MPFE in HMC | SDRAM scheduler in interconnect | SDRAM scheduler in interconnect |
| On-chip Debug and Trace Capabilities | No | No | Yes | Yes |