Differences Among Altera® SoC Device Families

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ID 683648
Date 8/29/2025
Public
Document Table of Contents
Document Table of Contents x
Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families x
Overview of HPS Modules HPS Micro Processor Unit Subsystem Differences Booting and Configuration Differences Cache Coherency Unit Differences Generic Interrupt Controller Differences HPS System Memory Management Unit Differences HPS On-Chip RAM Differences HPS Error Correction Differences HPS DMA Controller Differences HPS Clock Manager Differences HPS Reset Manager Differences HPS FPGA Manager Differences HPS System Manager Differences HPS Scan Manager Differences HPS Security Feature Differences HPS System Interconnect and Firewalls Differences HPS-FPGA Bridge Differences HPS General Purpose I/O Interface Differences I/O Pin Multiplexing Differences HPS Mailbox Differences HPS SDRAM Controller Subsystem Differences HPS NAND Flash Controller Differences HPS SD/eMMC Host Controller Differences Combo DLL PHY Differences HPS Quad SPI Flash Controller Differences HPS USB 2.0 OTG Controller Differences HPS USB 3.1 Gen1 Controller Differences HPS EMAC Differences HPS SPI Controller Differences HPS I2C Controller Differences I3C Controller Differences HPS UART Controller Differences HPS CAN Controller Differences HPS Timer Differences HPS Watchdog Timer Differences HPS CoreSight Debug and Trace Differences Revision History for Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families

HPS SPI Controller Differences

SPI Controller Feature Cyclone® V SoC,

Arria® V SoC

 Arria® 10 SoC Stratix® 10 SoC,

Agilex™ 7

F-Series/I-Series/

M-Series SoC

Agilex™ 5

E-Series/D-Series SoC,

Agilex™ 3

C-Series SoC
Synopsys IP Version 3.20a 3.22a 4.00a 4.00a
Number of SPI master cores 2 2 2 2
Number of SPI slave cores 2 2 2 2
Maximum master clock rate 60 MHz 60 MHz 60 MHz 60 MHz
Maximum slave clock rate 50 MHz 50 MHz 33.33 MHz 33.33 MHz
Programmable data frame size 4 to 16 bits 4 to 16 bits 4 to 32 bits 4 to 32 bits
SPI master bit rate clock ratio Fspi_m_clk ≥ 2 × max(Fsclk_out) Fl4_main_clk ≥ 2 ×max(Fsclk_out)
SPI slave bit rate clock ratio Fl4_main_clk ≥ 8 × max(Fsclk_in) Fl4_main_clk ≥ 12 × max(Fsclk_in)
Toggle slave select signal between frames when in SPI mode and SCPH=0? Yes Yes No (slave select signal stays low during data frames transfer) No (slave select signal stays low during data frames transfer)
Level Two Title