Differences Among Altera® SoC Device Families

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ID 683648
Date 8/29/2025
Public
Document Table of Contents
Document Table of Contents x
Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families x
Overview of HPS Modules HPS Micro Processor Unit Subsystem Differences Booting and Configuration Differences Cache Coherency Unit Differences Generic Interrupt Controller Differences HPS System Memory Management Unit Differences HPS On-Chip RAM Differences HPS Error Correction Differences HPS DMA Controller Differences HPS Clock Manager Differences HPS Reset Manager Differences HPS FPGA Manager Differences HPS System Manager Differences HPS Scan Manager Differences HPS Security Feature Differences HPS System Interconnect and Firewalls Differences HPS-FPGA Bridge Differences HPS General Purpose I/O Interface Differences I/O Pin Multiplexing Differences HPS Mailbox Differences HPS SDRAM Controller Subsystem Differences HPS NAND Flash Controller Differences HPS SD/eMMC Host Controller Differences Combo DLL PHY Differences HPS Quad SPI Flash Controller Differences HPS USB 2.0 OTG Controller Differences HPS USB 3.1 Gen1 Controller Differences HPS EMAC Differences HPS SPI Controller Differences HPS I2C Controller Differences I3C Controller Differences HPS UART Controller Differences HPS CAN Controller Differences HPS Timer Differences HPS Watchdog Timer Differences HPS CoreSight Debug and Trace Differences Revision History for Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families

HPS Clock Manager Differences

Clock Manager Feature Cyclone® V SoC,

Arria® V SoC

 Arria® 10 SoC Stratix® 10 SoC,

Agilex™ 7

F-Series/I-Series/

M-Series SoC

Agilex™ 5

E-Series/D-Series SoC,

Agilex™ 3

C-Series SoC
Number of phase-locked loop (PLL) blocks 3 2 2 2
HPS I/O clock inputs HPS_CLK1, HPS_CLK2 HPS_CLK1 HPS_OSC_CLK HPS_OSC_CLK
HPS I/O clock input location Fixed pin locations in HPS I/O Fixed pin locations in HPS dedicated I/O Can be assigned to any of the 48 dedicated I/Os Can be assigned to any of the 48 dedicated I/Os
HPS I/O clock signaling 1.8 V, 2.5 V, or 3.0 V LVCMOS 1.8 V, 2.5 V, or 3.0 V LVCMOS 1.8 V LVCMOS 1.8 V LVCMOS
HPS I/O functional test clock outputs No No Yes Yes7
7
Internal HPS PLL counter outputs on HPS dedicated I/O:
  • Two main counter clock outputs
  • Two peripheral counter clock outputs
  • One output for additional debug (such as PLL lock status)

Software can configure all test outputs through the MUX control registers.

Level Two Title