Differences Among Intel SoC Device Families

ID 683648
Date 8/22/2018
Public

HPS Clock Manager Differences

Clock Manager Feature Cyclone V SoC Arria V SoC Arria 10 SoC Stratix 10 SoC
Number of phase-locked loop (PLL) blocks 3 3 2 2
HPS I/O clock inputs HPS_CLK1, HPS_CLK2 HPS_CLK1, HPS_CLK2 HPS_CLK1 HPS_OSC_CLK
HPS I/O clock input location Fixed pin locations in HPS I/O Fixed pin locations in HPS I/O Fixed pin locations in HPS dedicated I/O Can be assigned to any of the 48 dedicated I/Os
HPS I/O clock signaling 1.8 V, 2.5 V, or 3.0 V LVCMOS 1.8 V, 2.5 V, or 3.0 V LVCMOS 1.8 V, 2.5 V, or 3.0 V LVCMOS 1.8 V LVCMOS
HPS I/O functional test clock outputs No No No Yes 11
11
Internal HPS PLL counter outputs on HPS dedicated I/O:
  • Two main counter clock outputs
  • Two peripheral counter clock outputs
  • One output for additional debug (such as PLL lock status)

Software can configure all test outputs through the MUX control registers.