Differences Among Altera® SoC Device Families

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ID 683648
Date 8/29/2025
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Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families x
Overview of HPS Modules HPS Micro Processor Unit Subsystem Differences Booting and Configuration Differences Cache Coherency Unit Differences Generic Interrupt Controller Differences HPS System Memory Management Unit Differences HPS On-Chip RAM Differences HPS Error Correction Differences HPS DMA Controller Differences HPS Clock Manager Differences HPS Reset Manager Differences HPS FPGA Manager Differences HPS System Manager Differences HPS Scan Manager Differences HPS Security Feature Differences HPS System Interconnect and Firewalls Differences HPS-FPGA Bridge Differences HPS General Purpose I/O Interface Differences I/O Pin Multiplexing Differences HPS Mailbox Differences HPS SDRAM Controller Subsystem Differences HPS NAND Flash Controller Differences HPS SD/eMMC Host Controller Differences Combo DLL PHY Differences HPS Quad SPI Flash Controller Differences HPS USB 2.0 OTG Controller Differences HPS USB 3.1 Gen1 Controller Differences HPS EMAC Differences HPS SPI Controller Differences HPS I2C Controller Differences I3C Controller Differences HPS UART Controller Differences HPS CAN Controller Differences HPS Timer Differences HPS Watchdog Timer Differences HPS CoreSight Debug and Trace Differences Revision History for Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families

Stratix 10 HPS Interface to SDM

Secure Device Feature Cyclone V SoC Arria V SoC Arria 10 SoC Stratix 10 SoC
Secure device manager implemented No No No Yes

The SDM is a hard subsystem in the FPGA portion of the Stratix 10 device that is responsible for:

  • Configuring the FPGA
  • Bootstrapping the HPS
  • Providing device-wide security features

The SDM is responsible for copying the HPS bootloader6 from its flash storage device to the on-chip RAM inside the HPS. Since the SDM is also used for configuration, the HPS can request that the SDM configure or reconfigure the FPGA. The SDM and HPS communicate with one another through the SDM interface, which is a bridge that exposes the address map of each subsystem to the other.

6 typically U-Boot or Unified Extensible Firmware Interface (UEFI)
Level Two Title