Differences Among Altera® SoC Device Families

Download PDF
ID 683648
Date 8/29/2025
Public
Document Table of Contents
Document Table of Contents x
Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families x
Overview of HPS Modules HPS Micro Processor Unit Subsystem Differences Booting and Configuration Differences Cache Coherency Unit Differences Generic Interrupt Controller Differences HPS System Memory Management Unit Differences HPS On-Chip RAM Differences HPS Error Correction Differences HPS DMA Controller Differences HPS Clock Manager Differences HPS Reset Manager Differences HPS FPGA Manager Differences HPS System Manager Differences HPS Scan Manager Differences HPS Security Feature Differences HPS System Interconnect and Firewalls Differences HPS-FPGA Bridge Differences HPS General Purpose I/O Interface Differences I/O Pin Multiplexing Differences HPS Mailbox Differences HPS SDRAM Controller Subsystem Differences HPS NAND Flash Controller Differences HPS SD/eMMC Host Controller Differences Combo DLL PHY Differences HPS Quad SPI Flash Controller Differences HPS USB 2.0 OTG Controller Differences HPS USB 3.1 Gen1 Controller Differences HPS EMAC Differences HPS SPI Controller Differences HPS I2C Controller Differences I3C Controller Differences HPS UART Controller Differences HPS CAN Controller Differences HPS Timer Differences HPS Watchdog Timer Differences HPS CoreSight Debug and Trace Differences Revision History for Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families

HPS On-Chip RAM Differences

Table 3.  On-Chip RAM Features
On-Chip RAM Features Cyclone® V SoC,

Arria® V SoC

 Arria® 10 SoC Stratix® 10 SoC,

Agilex™ 7

F-Series/I-Series/

M-Series SoC

Agilex™ 5

E-Series/D-Series SoC,

Agilex™ 3

C-Series SoC
On-Chip RAM size 64 KB 256 KB 256 KB 512 KB
ECC protection Basic Enhanced Enhanced Enhanced
ECC errors can be directly injected from the ECC controller N/A Yes Yes Yes
Table 4.  Comparison of Basic and Enhanced ECC Features
Features Basic ( Cyclone® V SoC,

Arria® V SoC)

 Enhanced ( Arria® 10 SoC, Stratix® 10 SoC, Agilex™ 7 SoC, Agilex™ 5 SoC, Agilex™ 3 SoC)
Single-bit error detection and correction Yes Yes
Double-bit error detection Yes Yes
Indirect memory access; for RAM testing and double-bit error correction No Yes
Logs most recent error memory address No Yes
Memory initialization block implements memory initialization No Yes
Single-bit error counter with programmable counter-match interrupt No Yes
Level Two Title