Differences Among Altera® SoC Device Families

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ID 683648
Date 8/29/2025
Public
Document Table of Contents
Document Table of Contents x
Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families x
Overview of HPS Modules HPS Micro Processor Unit Subsystem Differences Booting and Configuration Differences Cache Coherency Unit Differences Generic Interrupt Controller Differences HPS System Memory Management Unit Differences HPS On-Chip RAM Differences HPS Error Correction Differences HPS DMA Controller Differences HPS Clock Manager Differences HPS Reset Manager Differences HPS FPGA Manager Differences HPS System Manager Differences HPS Scan Manager Differences HPS Security Feature Differences HPS System Interconnect and Firewalls Differences HPS-FPGA Bridge Differences HPS General Purpose I/O Interface Differences I/O Pin Multiplexing Differences HPS Mailbox Differences HPS SDRAM Controller Subsystem Differences HPS NAND Flash Controller Differences HPS SD/eMMC Host Controller Differences Combo DLL PHY Differences HPS Quad SPI Flash Controller Differences HPS USB 2.0 OTG Controller Differences HPS USB 3.1 Gen1 Controller Differences HPS EMAC Differences HPS SPI Controller Differences HPS I2C Controller Differences I3C Controller Differences HPS UART Controller Differences HPS CAN Controller Differences HPS Timer Differences HPS Watchdog Timer Differences HPS CoreSight Debug and Trace Differences Revision History for Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families

HPS Reset Manager Differences

Reset Manager Feature Cyclone® V SoC,

Arria® V SoC

 Arria® 10 SoC

Stratix® 10 SoC,

Agilex™ 7

F-Series/I-Series/

M-Series SoC

Agilex™ 5

E-Series/D-Series SoC,

Agilex™ 3

C-Series SoC
Cold reset sources
  • POR monitor8
  • nPOR pin
  • FPGA fabric
  • FPGA CB 9 and scan manager
  • Software cold reset request
  • Security manager
  • nPOR pin
  • FPGA fabric
  • FPGA CB
  • Software cold reset request
  • SDM
  • HPS cold reset pin 10
  • HPS mailbox request to SDM
  • System watchdogs
  • SDM
  • HPS cold reset pin10
  • HPS or FPGA mailbox request to SDM
  • System watchdogs
Warm reset sources
  • nRST pin
  • FPGA fabric
  • Software warm reset request
  • MPU watchdogs
  • System watchdogs
  • nRST pin
  • FPGA fabric
  • Software warm reset request
  • MPU watchdogs
  • System watchdogs
  • SDM
  • FSBL 11 or software warm reset request
  • System watchdogs
  • (not supported) nRST pin
  • (not supported) FPGA mailbox message to SDM
  • SDM
  • FSBL11 or software warm reset request
  • System watchdogs
  • (not supported) nRST pin
  • (not supported) FPGA mailbox message to SDM
MPU/CPU cold reset — — COLDMODRST register CPUINRESET register
MPU/CPU warm reset — —
  • MPUMODRST register
  • Software request via RMR_EL3[RR] register
 Software request via RMR_EL3[RR] register
Debug reset resources
  • DAP 12 request
  • FPGA fabric
  • DAP request
  • FPGA fabric
  • DAP reset
  • DAP reset
RAM-clearing reset No Yes Handled by SDM Handled by SDM
Anti-tamper reset No Yes Handled by SDM Handled by SDM
8 Power-on reset
9 Control block
10 One of the dedicated SDM I/Os can be configured to work as an HPS cold reset pin
11 First-stage boot loader
12 Debug access port
Level Two Title