Differences Among Altera® SoC Device Families

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ID 683648
Date 8/29/2025
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Document Table of Contents
Document Table of Contents x
Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families x
Overview of HPS Modules HPS Micro Processor Unit Subsystem Differences Booting and Configuration Differences Cache Coherency Unit Differences Generic Interrupt Controller Differences HPS System Memory Management Unit Differences HPS On-Chip RAM Differences HPS Error Correction Differences HPS DMA Controller Differences HPS Clock Manager Differences HPS Reset Manager Differences HPS FPGA Manager Differences HPS System Manager Differences HPS Scan Manager Differences HPS Security Feature Differences HPS System Interconnect and Firewalls Differences HPS-FPGA Bridge Differences HPS General Purpose I/O Interface Differences I/O Pin Multiplexing Differences HPS Mailbox Differences HPS SDRAM Controller Subsystem Differences HPS NAND Flash Controller Differences HPS SD/eMMC Host Controller Differences Combo DLL PHY Differences HPS Quad SPI Flash Controller Differences HPS USB 2.0 OTG Controller Differences HPS USB 3.1 Gen1 Controller Differences HPS EMAC Differences HPS SPI Controller Differences HPS I2C Controller Differences I3C Controller Differences HPS UART Controller Differences HPS CAN Controller Differences HPS Timer Differences HPS Watchdog Timer Differences HPS CoreSight Debug and Trace Differences Revision History for Differences Among Altera® SoC Device Families
Differences Among Altera® SoC Device Families

HPS MPU Subsystem Differences

MPU Subsystem Feature Cyclone V SoC Arria V SoC Arria 10 SoC Stratix 10 SoC
CPU Single/Dual Cortex-A9 Dual Cortex-A9 Dual Cortex-A9 Quad Cortex-A53
Maximum frequency (MHz) 925 1050 1500 1500
Core revision r3p0 r3p0 r4p1-00rel0 r0p4-51rel0
L1 instruction cache 32 KB 32 KB 32 KB 32 KB
L1 data cache 32 KB 32 KB 32 KB 32 KB
L2 cache 512 KB 512 KB 512 KB 1 MB
ACP enabled Yes Yes Yes No 2
L1 data cache error checking Parity 3 Parity3 Parity3 ECC 4
L1 instruction cache error checking Parity3 Parity3 Parity3 Parity3 on data and tag bits
L2 cache error checking ECC5 ; ECC interrupts; optional parity3 for tag bits ECC5; ECC interrupts; optional parity 3 for tag bits ECC5; ECC interrupts; optional parity 3 for tag bits ECC5 on data and tag bits; ECC interrupts
Translation lookaside buffer (TLB) error checking Parity3 Parity3 Parity3 Parity3
Related Information
2 System level cache coherency is provided by the CCU. For details, please refer to the Cache Coherency Unit chapter of the Stratix 10 Hard Processor System Technical Reference Manual.
3 Single-bit error detection (SED)
4 Data: single-bit error correction, double-bit error detection (SECDED). Control bits: parity (SED)
5 SECDED with single-event upset (SEU) protection
Level Two Title