Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 4/01/2024
Public
Document Table of Contents

8.2.21. Port VHDL Type Properties

Name Description
AUTO The VHDL type of this signal is automatically determined. Single-bit signals are STD_LOGIC; signals wider than one bit are STD_LOGIC_VECTOR.
STD_LOGIC Indicates that the signal is not rendered in VHDL as a STD_LOGIC signal.
STD_LOGIC_VECTOR Indicates that the signal is rendered in VHDL as a STD_LOGIC_VECTOR signal.