Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 4/01/2024
Public

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4.5.1.1. Inserting Pipeline Bridges

You can insert an Avalon® memory mapped pipeline bridge to insert registers in the path between the bridges and its host and agents. If a critical register-to-register delay occurs in the interconnect, a pipeline bridge can help reduce this delay and improve system fMAX.

The Avalon® memory mapped pipeline bridge component integrates into any Platform Designer system. The pipeline bridge options can increase logic utilization and read latency. The change in topology may also reduce concurrency if multiple hosts arbitrate for the bridge. You can use the Avalon® memory mapped pipeline bridge to control topology without adding a pipeline stage. A pipeline bridge that does not add a pipeline stage is optimal in some latency-sensitive applications. For example, a CPU may benefit from minimal latency when accessing memory.

Figure 163.  Avalon® Memory Mapped Pipeline Bridge