R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/19/2022

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2.3. PCIe Hard IP Mode

In this mode, the four cores (one x16 core, one x8 core and two x4 cores) in the PCIe Hard IP can be configured to support the following topologies:

Table 10.  Configuration Modes Supported by the R-tile Avalon Streaming Intel FPGA IP for PCI Express
Configuration Mode Native IP Mode Endpoint (EP) / Root Port (RP) / TLP Bypass (BP) Active Hard IP Cores
Configuration Mode 0 Gen3 x16 or Gen4 x16 or Gen5 x16 EP/RP/BP x16
Configuration Mode 1 Gen3 x8/Gen3 x8 or Gen4 x8/Gen4 x8 or Gen5 x8/Gen5 x8 EP/RP/BP x16, x8
Configuration Mode 2 Gen3 x4/Gen3 x4/Gen3 x4/Gen3 x4 or Gen4 x4/Gen4 x4/Gen4 x4/Gen4 x4 or Gen5 x4/Gen5 x4/Gen5 x4/Gen5 x4 EP/RP/BP x16, x8, x4_0, x4_1
Configuration Mode 3 PIPE Direct (with a maximum of 16 channels) N/A None

In Configuration Mode 0, only the x16 core is active, and it operates in x16 mode (in Gen3, Gen4 or Gen5).

In Configuration Mode 1, the x16 core and x8 core are active, and they operate as two Gen3 x8 cores, two Gen4 x8 cores or two Gen5 x8 cores.
Note: In Configuration Mode 1, when you use only one of the x8 bifurcated ports, you must ensure that the other bifurcated port's lanes are not physically connected. If you connect both x8 bifurcated ports to a x16 Root Port/Switch device, it is non-deterministic which x8 port will be trained.
In Configuration Mode 2, all four cores (x16, x8, x4_0, x4_1) are active, and they operate as four Gen3 x4 cores, four Gen4 x4 cores or four Gen5 x4 cores.
Note: In Configuration Mode 2, for the 22.1 release of Intel® Quartus® Prime, the x4_0 core is disabled for devices without R2 or R3 in their OPN. For these devices, the maximum number of active x4 cores for Configuration Mode 2 is three (with these active cores being the x16, x8 and x4_1 cores, all configured as x4 cores). However, devices with the R2 or R3 suffix in their OPN number can support the x16, x8, x4_1 and x4_0 cores all being active while in Configuration Mode 2. For additional details on OPN decoding, refer to the Intel® Agilex™ FPGAs and SoCs Device Overview.

Each of the cores has its own Avalon® -ST interface to the user logic. The number of IP-to-User Logic interfaces exposed to the FPGA fabric are different based on the configuration modes.