R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/19/2022

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Document Table of Contents Receive Signals

Table 81.  PIPE Direct EMIB Data Channel Receive SignalsIn the signal names, X is the lane number and ranges from 0 to 15.
Signal Names Direction Descriptions/Notes Clock Domain
lnX_pipe_direct_rxdatavalid1_o Output This signal qualifies rxdata[63:32]. lnX_pipe_direct_pld_rx_clk_out_o
lnX_pipe_direct_rxdatavalid0_o Output This signal qualifies rxdata[31:0]. lnX_pipe_direct_pld_rx_clk_out_o
lnX_pipe_direct_rxdata_o[63:0] Output Receive data bus lnX_pipe_direct_pld_rx_clk_out_o
lnX_pipe_direct_rxelecIdle_o Output This signal indicates the receiver detection of an Electrical Idle. It is an asynchronous signal.
Note: This signal may toggle during continuous traffic. Per the PIPE Spec 5.1.1 section 9.4, the Soft IP controller must not rely on this signal for Electrical Idle detection when operating at gen2 or higher speeds. This toggling may not be observed in simulation and is a known limitation of the R-tile simulation model.

The following timing diagrams provide an illustration of the behaviors of the PIPE Direct RX Datapath signals:

Figure 42. PIPE Direct RX Datapath
Note: At Gen1 and Gen2 speeds, only the 10 LSB bits in the upper and lower segments of the LnX_pipe_direct_rxdata_o bus contain valid data. Bits [31:10] and [63:42] are don't-cares.