R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/19/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1.1. Debugging Link Training Issues

The Physical Layer automatically performs link training and initialization without software intervention. This is a well-defined process to configure and initialize the device's Physical Layer and link so that PCIe packets can be transmitted.

Some examples of link training issues may include:
  • Link fails to negotiate to the expected link speed.
  • Link fails to negotiate to the expected link width.
  • LTSSM fails to reach/stay stable at L0.

Use the flow chart below to identify the potential cause of a link training problem when using the R-Tile Avalon-ST IP for PCI Express.

Figure 55. Link Training Debug Flow
Note: To reinitiate the equalization procedure, write 1b to the Perform Equalization bit [0] in the Link Control 3 register.