R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/19/2022

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Document Table of Contents Avalon® Streaming TX Interface pX_tx_st_ready_o Behavior

The following timing diagram illustrates the behavior of pX_tx_st_ready_o, which is deasserted to pause the data transmission to the R-tile PCI Express IP core, and then reasserted. As an example, the timing diagram shows a readyLatency of three cycles. The application deasserts pX_tx_stN_valid_i three cycles after pX_tx_st_ready_o is deasserted. Refer to the Avalon® Interface Specifications for a detailed definition of readyLatency.

The maximum latency between the deassertion of pX_tx_st_ready_o and pX_tx_stN_valid_i is 16 cycles.

The application must not deassert pX_tx_stN_valid_i between pX_tx_stN_sop_i and pX_tx_stN_eop_i on a ready cycle unless there is backpressure from the R-tile PCIe IP indicated by the deassertion of pX_tx_st_ready_o. For the definition of a ready cycle, refer to the Avalon Interface Specifications.

Note: Failing to meet this guideline may cause the transmission of a TLP with an invalid LCRC.
Note: This is an additional requirement for the R-tile PCI Express IP core that does not follow the Avalon® -ST standard.
Figure 31.  Avalon® Streaming TX Interface pX_tx_st_ready_o Behavior