Visible to Intel only — GUID: vfi1613585239431
Ixiasoft
Visible to Intel only — GUID: vfi1613585239431
Ixiasoft
2.3.1. Clocking
- PHY clock domain (i.e. core_clk domain): this clock is synchronous to the SerDes parallel clock.
- EMIB/FPGA fabric interface clock domain (i.e. pld_clk domain): this clock is derived from the same reference clock (refclk0) as the one used by the SerDes. However, this clock is generated from a stand-alone core PLL.
- Application clock domain (coreclkout_hip) for in-band signals: this clock is an output from the R-tile IP, and it has the same frequency as pld_clk.
- Application clock domain (slow_clk) for sideband signals: this clock is another output from the R-tile IP. It is a divide-by-2/4 version of coreclkout_hip.
Mode | PHY Clock Frequency | Application Clock Frequency |
---|---|---|
PCIe Gen1 | 1000 MHz | Gen1 is supported only via link down-training and not natively. Hence, the application clock frequency depends on the configuration you choose in the IP Parameter Editor. For example, if you choose a Gen3 configuration, the application clock frequency is 250 MHz - 300 MHz. |
PCIe Gen2 | 1000 MHz | Gen2 is supported only via link down-training and not natively. Hence, the application clock frequency depends on the configuration you choose in the IP Parameter Editor. For example, if you choose a Gen3 configuration, the application clock frequency is 250 MHz - 300 MHz. |
PCIe Gen3 | 1000 MHz | 250 MHz - 500 MHz (*) |
PCIe Gen4 | 1000 MHz | 250 MHz - 500 MHz (*) |
PCIe Gen5 | 1000 MHz | 400 MHz - 500 MHz |
R-tile has two reference clock inputs at the package level, refclk0 and refclk1. You must connect a 100 MHz reference clock source to these two inputs. Depending on the port mode, you can drive the two refclk inputs using either a single clock source or two independent clock sources.
In 1x16 and 4x4 modes, drive the refclk inputs with a single clock source (through a fanout buffer) as shown in the figure below.
- If the link can handle two separate reference clocks, drive the refclk0 of R-tile with the on-board free-running oscillator.
- If the link needs to use a common reference clock, then PERST# needs to indicate the stability of this reference clock. If this reference clock goes down, the entire R-tile must be reset.
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