R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/19/2022
Public
Document Table of Contents

1.1.1. Standards and Specifications Compliance

  • PCI Express Base Specification Revision 5.0, Version 1.0
    Note: Throughout this document, the term GenN may be used to refer to the PCI Express Base Specification Revision N.
    Table 1.  Terminology
    Terms Specifications
    Gen1 PCI Express Base Specification Revision 1.0
    Gen2 PCI Express Base Specification Revision 2.0
    Gen3 PCI Express Base Specification Revision 3.0
    Gen4 PCI Express Base Specification Revision 4.0
    Gen5 PCI Express Base Specification Revision 5.0
  • Single Root I/O Virtualization and Sharing Specification, Revision 1.1
  • Address Translation Services, Revision 1.1
  • Virtual I/O Device (VIRTIO) Version 1.0
  • PHY Interface for PCI Express Specification, Version 5.1.1
    Note: This interface is accessible when the IP is in PIPE mode.

Did you find the information on this page useful?

Characters remaining:

Feedback Message