R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/19/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3.1. Overview

When the TLP Bypass feature is enabled, the R-tile Avalon® -ST IP does not process received TLPs internally but outputs them to the user application (this includes the processing of Configuration TLPs, which are forwarded to the application logic). This allows the application to implement a custom Transaction Layer.

When in TLP Bypass mode, the same Avalon® Streaming interface is used. This includes the regular Tx and Rx interfaces along with their corresponding flow control interfaces for the credit handling. In addition, although most of the transaction layer is bypassed, there is a Lite Transaction Layer still active which interfaces with the application logic through the Hard IP Reconfiguration Interface to access the set of PCIe registers related to link operation that continues to be implemented on the R-tile Avalon® Streaming IP. This set of registers is referred to in the figure below as the Lite PCIe Configuration Space. For details on these registers, refer to Hard IP Reconfiguration Interface.
Figure 20. R-tile Avalon® -ST IP in TLP Bypass Mode

In TLP bypass mode, R-tile supports the autonomous Hard IP feature. It responds to configuration accesses before the FPGA fabric enters user mode with Completions with a CRS code.

Note that in TLP Bypass mode, the PCIe Hard IP does not generate/check the ECRC. However, you can enable the IP to remove it if the received TLP has the ECRC. The steps on how to do this are described in section ECRC.

Note: In TLP bypass mode, CvP init and update are not supported.