R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/19/2022
Document Table of Contents Deferrable Memory Write (DMWr)

Deferrable Memory Write (DMWr) transactions are a new type of TLP supported by the PCI Specifications. This new feature allows the completer to return an acknowledgement to the requester of the DMWr transaction and provides the completer a mechanism to temporarily refuse the request. For additional details, refer to the Deferrable Memory Write (DMWr) ECN.

In the R-tile Avalon Streaming Intel FPGA IP for PCIe, the requirements for supporting this Deferrable Memory Write feature are:
  1. During the credit initialization phase between the IP and the Application logic, the Application logic needs to advertise infinite credits for Non-Posted Data (NPD) transactions to the IP. Note that the Application logic can still throttle the Non-Posted traffic with the credits for the Non-Posted Headers (NPH). Refer to Credit Initialization for more details on the procedure required to advertise infinite credits.
  2. With infinite credits being advertised between the R-tile Avalon Streaming IP and the Application logic, the minimum size of the Application logic Rx buffer for Non-Posted Data (NPD) transactions needs to be equal to the amount of Non-Posted Header (NPH) advertised credits multiplied by 128 bytes.
Note: DMWr support is only available in devices with the suffix R2 or R3 in their OPN numbers. For more details on OPN decoding, refer to the Intel® Agilex™ FPGAs and SoCs Device Overview.

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