R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/19/2022

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Document Table of Contents D3Hot Exit Initiated by Host

The system host will attempt to send a CfgWr to the Power Management Control register to go to D0. This will automatically first cause a transition from L1 to L0 started by the host. Then, the CfgWr will be sent to the Power Management Control register in the R-Tile Avalon® Streaming Intel FPGA IP for PCIe to change the power state and pme enable. Alternatively, the host can initiate a link retrain, link disable or hot reset for an L1 exit.