R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/19/2022

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2.4.2. Reset

There is only one PERST# pin ( pin_perst_n) on the R-tile. Therefore, toggling pin_perst_n will affect the entire R-tile. This pin also resets the EMIB interface. If the R-tile x16 port is bifurcated into multiple ports, toggling pin_perst_n will affect all the ports . To reset each port individually, use the pin_perst_n in conjunction with the individual lane resets (lnX_pipe_direct_pld_pcs_rst_n_i).

The lnX_pipe_direct_pld_pcs_rst_n_i signals reset the per-lane TX/RX interfaces.

In case your Soft IP Controller is only using lanes 8-15, it is required to perform part of the reset sequence on lane 0 until one of the 8-15 lanes has completed its reset sequence. For further details regarding the reset sequence, refer to PIPE Direct Reset Sequence.

In PIPE mode, the per-lane lnX_pipe_direct_pld_pcs_rst_n_i signals must be gated by the per-lane lnX_pipe_direct_tx_transfer_en_o signal.

For more details, refer to PIPE Direct Mode.