R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/19/2022

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4.3.4. Hard IP Reconfiguration Interface

This interface is an Avalon® -MM slave interface with a 32‑bit address and an 8‑bit data bus. You can use this interface to dynamically modify the value of configuration registers. Note that after a warm reset or cold reset, changes made to the configuration registers of the Hard IP via this interface are lost as these registers revert back to their default values.

Note: This interface can be used in Endpoint, Root Port and TLP Bypass modes. However, it must be enabled if Root Port or TLP Bypass mode is selected.

In Root Port mode, the application logic uses this interface to access its PCIe configuration space to perform link control functions (such as Hot Reset, link disable, or link retrain).

In TLP Bypass mode, the Hard IP forwards the received Type0/1 Configuration request TLPs to the application logic, which must respond with Completion TLPs with a status of Successful Completion (SC), Unsupported Request (UR), Configuration Request Retry Status (CRS), or Completer Abort (CA). If a received Configuration request TLP needs to update a PCIe configuration space register, the application logic needs to use the Hard IP Reconfiguration interface to access that PCIe configuration space register.

Table 67.  Hard IP Reconfiguration Interface Signals
Signal Name Direction Description EP/RP/BP Clock
pX_hip_reconfig_readdata_o[7:0] where X = 0, 1, 2, 3 Output Avalon® -MM read data outputs EP/RP/BP slow_clk
pX_hip_reconfig_readdatavalid_o where X = 0, 1, 2, 3 Output Avalon® -MM read data valid. When asserted, this signal indicates that the data on hip_reconfig_readdata_o[7:0] is valid. EP/RP/BP slow_clk
pX_hip_reconfig_write_i where X = 0, 1, 2, 3 Input Avalon® -MM write enable EP/RP/BP slow_clk
pX_hip_reconfig_read_i where X = 0, 1, 2, 3 Input Avalon® -MM read enable.
Note: This interface is not pipelined. User application must wait for the return of the data from the current read (on hip_reconfig_readdata_o[7:0]) before starting another read operation.
EP/RP/BP slow_clk
pX_hip_reconfig_address_i[31:0] where X = 0, 1, 2, 3 Hard IP Reconfiguration Interface When Performing a Read Operation Input

Avalon® -MM reconfiguration address.

Following is the mapping for the pX_hip_reconfig_address_i[31:0] bus:
  • Virtual Function Number: pX_hip_reconfig_address_i[31:21].
  • Reserved (must be set to 0): pX_hip_reconfig_address_i[20]
  • Physical Function Number: pX_hip_reconfig_address_i[19:17].
  • Virtual Function Active: pX_hip_reconfig_address_i[16].
  • Register Offset (please refer to the column Address Offset that is available in the linked collateral in Configuration Space Registers): pX_hip_reconfig_address_i[15:0]
  • Example 1: To access the MSI-X Capability Structure for PF1 with SR-IOV disabled, set the pX_hip_reconfig_address_i to 0x0002_00B0.
  • Example 2: To access the MSI-X Capability Structure for PF0, set the pX_hip_reconfig_address_i to 0x0021_00B0.
EP/RP/BP slow_clk
pX_hip_reconfig_writedata_i[7:0] where X = 0, 1, 2, 3 Input Avalon® -MM write data inputs EP/RP/BP slow_clk
pX_hip_reconfig_waitrequest_o where X = 0, 1, 2, 3 Output When asserted, this signal indicates the IP core is not ready to respond to a request. EP/RP/BP slow_clk

As an example, Hard IP Reconfiguration Interface when performing a read operation shows the behavior of the Hard IP Reconfiguration Interface when performing a read operation to the Current Link Speed and Negotiated Link Width fields of the Link Status Register, when the R-Tile Avalon Streaming Intel FPGA IP for PCIe is configured in Gen5 x16 mode with a single physical function enabled. For additional details on configuration space registers, refer to Configuration Space Registers.

Figure 35. Hard IP Reconfiguration Interface when performing a read operation