R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/19/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Credit Initialization

Each side will initialize its credit counters during the initialization stage. In this stage, the sink communicates its total buffer size available to the source. The sink initiates the initialization phase by asserting the *crdt_init signal. If the source is ready for initialization, it asserts *crdt_init_ack in response. After receiving *crdt_init_ack, the sink asserts the *crdt_update signal to communicate the buffer size available to receive transactions.

The source increments its internal credit counter by *crdt_update_cnt for every cycle it encounters an assertion of the *update signal for the header credit.

The deassertion of *init signals the completion of the initialization phase. There is a required minimum of 2 clock cycles separation between the deassertion of the *update and *init signals.

Figure 27. Credit Initialization
Note: The internal signals in the figure above are not exposed to the application logic.

Re-initialization is generally not required. However, if required (for example, if the application logic wants to change the buffer size), it can be done only when the source and sink are both in IDLE state. The IDLE state for the sink is when its receiver buffer is empty. For the source, the IDLE state is when it has nothing to transmit when the initialization request is made.