4.3. PCI Express Mode
- p0 : x16 core
- p1 : x8 core
- p2 : x4_0 core
- p3 : x4_1 core
R-tile Top-Level Block Diagram in PCI Express Mode below shows the top-level signals of this IP. Note that the signal names in the figure will get the appropriate prefixes pn (where n = 0, 1, 2 or 3) depending on which of the supported topologies (x16, x8x8, x4x4x4x4) the R-tile Avalon® streaming Intel FPGA IP for PCIe is in.
The only cases where the interface signal names do not get the pn prefixes are the interfaces that are common for all the cores, like clocks and resets.
pX: X is port number, ranges from 0 to 3.
stN: N is segment number, ranges from 0 to 3.
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