1. About the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express 2. IP Architecture and Functional Description 3. Advanced Features 4. Interfaces 5. Parameters 6. Troubleshooting/Debugging 7. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide Archives 8. Document Revision History for the R-Tile Avalon® Streaming Intel FPGA IP for PCI Express User Guide A. Configuration Space Registers B. Root Port Enumeration C. Implementation of Address Translation Services (ATS) in Endpoint Mode D. Packets Forwarded to the User Application in TLP Bypass Mode
18.104.22.168.1. VirtIO Common Configuration Capability Register (Address: 0x012) 22.214.171.124.2. VirtIO Common Configuration BAR Indicator Register (Address: 0x013) 126.96.36.199.3. VirtIO Common Configuration BAR Offset Register (Address: 0x014) 188.8.131.52.4. VirtIO Common Configuration Structure Length Register (Address 0x015) 184.108.40.206.5. VirtIO Notifications Capability Register (Address: 0x016) 220.127.116.11.6. VirtIO Notifications BAR Indicator Register (Address: 0x017) 18.104.22.168.7. VirtIO Notifications BAR Offset Register (Address: 0x018) 22.214.171.124.8. VirtIO Notifications Structure Length Register (Address: 0x019) 126.96.36.199.9. VirtIO Notifications Notify Off Multiplier Register (Address: 0x01A) 188.8.131.52.10. VirtIO ISR Status Capability Register (Address: 0x02F) 184.108.40.206.11. VirtIO ISR Status BAR Indicator Register (Address: 0x030) 220.127.116.11.12. VirtIO ISR Status BAR Offset Register (Address: 0x031) 18.104.22.168.13. VirtIO ISR Status Structure Length Register (Address: 0x032) 22.214.171.124.14. VirtIO Device Specific Capability Register (Address: 0x033) 126.96.36.199.15. VirtIO Device Specific BAR Indicator Register (Address: 0x034) 188.8.131.52.16. VirtIO Device Specific BAR Offset Register (Address 0x035) 184.108.40.206.17. VirtIO Device Specific Structure Length Register (Address: 0x036) 220.127.116.11.18. VirtIO PCI Configuration Access Capability Register (Address: 0x037) 18.104.22.168.19. VirtIO PCI Configuration Access BAR Indicator Register (Address: 0x038) 22.214.171.124.20. VirtIO PCI Configuration Access BAR Offset Register (Address: 0x039) 126.96.36.199.21. VirtIO PCI Configuration Access Structure Length Register (Address: 0x03A) 188.8.131.52.22. VirtIO PCI Configuration Access Data Register (Address: 0x03B)
4.3.1. Avalon® Streaming Interface 4.3.2. Precision Time Measurement (PTM) Interface (Endpoint Only) 4.3.3. Interrupt Interface 4.3.4. Hard IP Reconfiguration Interface 4.3.5. Error Interface 4.3.6. Completion Timeout Interface 4.3.7. Configuration Intercept Interface 4.3.8. Power Management Interface 4.3.9. Hard IP Status Interface 4.3.10. Page Request Services (PRS) Interface (Endpoint Only) 4.3.11. Function-Level Reset (FLR) Interface (Endpoint Only) 4.3.12. SR-IOV VF Error Flag Interface (Endpoint Only) 4.3.13. General Purpose VSEC Interface
184.108.40.206. Device Capabilities 220.127.116.11. VirtIO Parameters 18.104.22.168. Link Capabilities 22.214.171.124. Legacy Interrupt Pin Register 126.96.36.199. MSI Capabilities 188.8.131.52. MSI-X Capabilities 184.108.40.206. Slot Capabilities 220.127.116.11. Latency Tolerance Reporting (LTR) 18.104.22.168. Process Address Space ID (PASID) 22.214.171.124. Device Serial Number Capability 126.96.36.199. Page Request Service (PRS) 188.8.131.52. Access Control Service (ACS) 184.108.40.206. Power Management 220.127.116.11. Vendor Specific Extended Capability (VSEC) Registers 18.104.22.168. TLP Processing Hints (TPH) 22.214.171.124. Address Translation Services (ATS) Capabilities 126.96.36.199. Precision Time Management (PTM)
8. Document Revision History for the R-Tile Avalon® Streaming Intel FPGA IP for PCI Express User Guide
188.8.131.52. Data Link Layer Overview
The Data Link Layer (DLL) is located between the Transaction Layer and the Physical Layer. It maintains packet integrity and communicates (by DLL packet transmission) at the PCI Express link level.
The DLL implements the following functions:
- Link management through the reception and transmission of DLL Packets (DLLP), which are used for the following functions:
- Power management of DLLP reception and transmission
- To transmit and receive ACK/NAK packets
- Data integrity through the generation and checking of CRCs for TLPs and DLLPs
- TLP retransmission in case of NAK DLLP reception or replay timeout, using the retry (replay) buffer
- Management of the retry buffer
- Link retraining requests in case of error through the Link Training and Status State Machine (LTSSM) of the Physical Layer
Figure 10. Data Link Layer
The DLL has the following sub-blocks:
- Data Link Control and Management State Machine—This state machine connects to both the Physical Layer’s LTSSM state machine and the Transaction Layer. It initializes the link and flow control credits and reports status to the Transaction Layer.
- Power Management—This function handles the handshake to enter low power mode. Such a transition is based on register values in the Configuration Space and received Power Management (PM) DLLPs. For more details on the power states supported by the R-Tile Avalon® -ST IP for PCIe, refer to section Power Management Interface.
- Data Link Layer Packet Generator and Checker—This block is associated with the DLLP’s 16-bit CRC and maintains the integrity of transmitted packets.
- Transaction Layer Packet Generator—This block generates transmit packets, including a sequence number and a 32-bit Link CRC (LCRC). The packets are also sent to the retry buffer for internal storage. In retry mode, the TLP generator receives the packets from the retry buffer and generates the CRC for the transmit packet.
- Retry Buffer—The retry buffer stores TLPs and retransmits all unacknowledged packets in the case of NAK DLLP reception. In case of ACK DLLP reception, the retry buffer discards all acknowledged packets.
- ACK/NAK Packets—The ACK/NAK block handles ACK/NAK DLLPs and generates the sequence number of transmitted packets.
- Transaction Layer Packet Checker—This block checks the integrity of the received TLP and generates a request for transmission of an ACK/NAK DLLP.
- TX Arbitration—This block arbitrates transactions, prioritizing in the following order:
- Initialize FC Data Link Layer packet
- ACK/NAK DLLP (high priority)
- Update FC DLLP (high priority)
- PM DLLP
- Retry buffer TLP
- Update FC DLLP (low priority)
- ACK/NAK FC DLLP (low priority)
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