R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 3/28/2022
Public

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4.5.1.2. Receive Signals

Table 77.  PIPE Direct EMIB Data Channel Receive SignalsIn the signal names, X is the lane number and ranges from 0 to 15.
Signal Names Direction Descriptions/Notes Clock Domain
lnX_pipe_direct_rxdatavalid1_o Output This signal qualifies rxdata[63:32]. lnX_pipe_direct_pld_rx_clk_out_o
lnX_pipe_direct_rxdatavalid0_o Output This signal qualifies rxdata[31:0]. lnX_pipe_direct_pld_rx_clk_out_o
lnX_pipe_direct_rxdata_o[63:0] Output Receive data bus lnX_pipe_direct_pld_rx_clk_out_o
lnX_pipe_direct_rxelecIdle_o Output This signal indicates the receiver detection of an Electrical Idle. It is an asynchronous signal.
Note: This signal may toggle during continuous traffic. Per the PIPE Spec 5.1.1 section 9.4, the Soft IP controller must not rely on this signal for Electrical Idle detection when operating at gen2 or higher speeds. This toggling may not be observed in simulation and is a known limitation of the R-tile simulation model.
Async
lnX_pipe_direct_rxstandbystatus_o Output

Indicates whether the PHY is active or in standby mode.

  • 0 = Active
  • 1 = Standby
pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_pclkratechangeok_o Output

This signal is asserted by the PHY when it is ready for the MAC to change the clock rate.

pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_rxstatus_o Output

Reflects the state of the high-speed receiver. A 1 on this bit indicates Rx is detected.

Note: The only status applicable to the PIPE SerDes architecture mode is "Receiver detected".
pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_phystatus_o Output Indicates the completion of several PHY functions including stable PCLK, after reset deassertion, power management state transitions, rate change and receiver detection. pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_cdrlockstatus_o Output
This is the Receiver CDR lock indicator.
  • 0 = CDR is not locked and is not at the correct frequency.
  • 1 = CDR is at the correct frequency.

If this signal is deasserted when it is expected to be asserted, it indicates a fault condition and the receiver should be reset.

Async
lnX_pipe_direct_cdrlock2data_o Output
This is the Receiver CDR data lock indicator.
  • 0 = CDR is not locked to the data.
  • 1 = CDR is locked to the data. RX data is valid.
Async

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