R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 3/28/2022
Public

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4.4.6. Completion Timeout Interface

The R-Tile IP for PCIe features a Completion timeout mechanism to keep track of Non-Posted requests sent by the user application and the corresponding Completions received. When the R-Tile IP detects a Completion timeout, it notifies the user application by asserting the cpl_timeout_o signal.

When a Completion timeout happens, the user application can use the Completion Timeout Interface (for each port) to get more detailed information about the event and update the AER capability registers if required. After the completion timeout FIFO becomes empty, the IP core deasserts the cpl_timeout_o signal.

Table 65.  Completion Timeout Interface Signals
Signal Name Direction Description EP/RP/BP Clock Domain
pX_cpl_timeout_o Output Indicates that the Completion TLP for a request has not been received within the expected time window. The outputs below are valid when cpl_timeout_o is asserted. EP/RP/BP slow_clk
pX_cpl_timeout_func_num_o[2:0] Output The function number of the timed-out completion. EP/RP/BP slow_clk
pX_cpl_timeout_vfunc_num_o[10:0] Output Indicates which virtual function (VF) had a completion timeout. EP/RP/BP slow_clk
pX_cpl_timeout_vfunc_active_o Output Indicates that a virtual function (VF) had a completion timeout. EP/RP/BP slow_clk
pX_cpl_timeout_cpl_tc_o[2:0] Output The Traffic Class of the timed-out completion. EP/RP/BP slow_clk
pX_cpl_timeout_cpl_attr_o[1:0] Output The Attributes field of the timed-out completion. EP/RP/BP slow_clk
pX_cpl_timeout_cpl_len_o[11:0] Output The length (in bytes) of the timed-out completion. EP/RP/BP slow_clk
pX_cpl_timeout_cpl_tag_o[9:0] Output The Tag field of the timed-out completion. EP/RP/BP slow_clk

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