R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.4.2. Reset

There is only one PERST# pin ( pin_perst_n) on the R-tile. Therefore, toggling pin_perst_n will affect the entire R-tile. This pin also resets the EMIB interface. If the R-tile x16 port is bifurcated into multiple ports, toggling pin_perst_n will affect all the ports . To reset each port individually, use the pin_perst_n in conjunction with the individual lane resets (lnX_pipe_direct_pld_pcs_rst_n_i).

The lnX_pipe_direct_pld_pcs_rst_n_i signals reset the per-lane TX/RX interfaces.

In PIPE mode, the per-lane lnX_pipe_direct_pld_pcs_rst_n_i signals must be gated by the per-lane lnX_pipe_direct_tx_transfer_en_o signal.

For more details, refer to PIPE Direct Mode.

Did you find the information on this page useful?

Characters remaining:

Feedback Message