The R-Tile Avalon® -ST IP for PCI Express contains Physical Medium Attachment (PMA) and PCI Express Physical Coding Sublayer (PCIe PCS) blocks for handling the Physical layer (PHY) packets. The PMA receives and transmits high-speed serial data on the serial lanes. The PCS acts as an interface between the PMA and the PCIe controller, and performs functions like data encoding and decoding, scrambling and descrambling, block synchronization etc. The PCS and PCIe controller are only available when the PCIe Hard IP mode is used. Refer to PIPE Direct Mode for a functional description of the PIPE mode.
The R-tile PMA consists of two octets. Each octet contains a pair of transmit PLLs and eight SerDes lanes capable of running up to 32 GT/s to perform the various TX and RX functions.
The Slow PLL generates the required transmit clocks for Gen1/Gen2 speeds, while the Fast PLL generates the required clocks for Gen3/Gen4/Gen5 speeds.
The PMA performs functions such as serialization/deserialization, clock data recovery, and analog front-end functions such as Continuous Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE) and transmit equalization.
The transmitter consists of a 3-tap equalizer with one tap of pre-cursor, one tap of main cursor and one tap of post-cursor.
The receiver consists of attenuation (ATT), CTLE, Voltage gain amplifier (VGA) and DFE blocks that are adaptive for Gen3/Gen4/Gen5 speeds. RX Lane Margining is supported by the PHY. The Lane Margining supports timing and voltage margining.
- Maximum Timing Offset: -0.5UI to +0.5UI
- Number of timing steps: 63
- Independent left and right timing margining is not supported.
- Independent Error Sampler is not supported (lane margining may produce logical errors in the data stream and cause the LTSSM to go to the Recovery state).
- Maximum Voltage Offset: -120mV to +120mV
- Number of voltage steps: 127
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