R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 3/28/2022

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2.4.1. Clocking

In PIPE Direct mode, the PCS, Data Link Layer and Transaction Layer inside the R-tile IP for PCIe are not active. The only clock domains are pipe_direct_pld_tx_clk_out_o and lnX_pipe_direct_pld_rx_clk_out_o, which are clock outputs from the R-tile PHY layer to the FPGA fabric.

Figure 10. Clock Domains in PIPE Mode
Table 11.  PHY Clock and Application Clock Frequencies
Mode PHY Clock Frequency Application Clock Frequency
PIPE Direct TX: 1000 MHz

TX: 500 MHz


Gen1: 250 MHz

Gen2: 500 MHz

Gen3: 250 MHz

Gen4: 500 MHz

Gen5: 1000 MHz


Gen1: 125 MHz

Gen2: 250 MHz

Gen3: 125 MHz

Gen4: 250 MHz

Gen5: 500 MHz

R-tile has two reference clock inputs at the package level, refclk0 and refclk1.

You must connect a 100 MHz reference clock source to these two inputs. In PIPE Direct mode, you must drive the two refclk inputs from the same clock source. However, if Octet 1 is not used, refclk1 can be tied to ground.

Figure 11. Using a Single 100 MHz Clock Source (for Endpoint and Root Port)

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