R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 3/28/2022
Public

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3.2.2.5.20. VirtIO PCI Configuration Access BAR Offset Register (Address: 0x039)

This register indicates where the structure begins relative to the base address associated with the BAR. The alignment requirements of the offset are indicated in each structure-specific section.

Table 38.  VirtIO PCI Configuration Access BAR Offset Register
Bit Location Description Access Type Default Value
31:0 BAR Offset RW Undefined

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