R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 3/28/2022
Public

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4.5.4. PIPE Direct Reset Sequence

In PIPE Direct mode, your application logic is responsible for managing most of the PHY reset sequence in the FPGA fabric. The following figure describes the required sequence.

Figure 37. PIPE Direct Reset Sequence

Below are the steps required for the reset sequence and the TX/RX data transfer for lane 0 in the R-Tile Avalon Streaming IP when configured in PIPE-D mode. This behavior applies in the same way for other lanes.

Please note that each of the required steps correlates with the corresponding letter in the waveforms.

For the TX path:
  1. Step (a) : ninit_done is driven low by the Reset Release IP indicating the FGPA fabric is configured. The Soft IP controller should be in reset until this signal is low.
  2. Step (b) : pin_perst_n_o is driven high by the R-Tile Avalon Streaming IP. This signal reflects the PERTS# signal at the board level.
  3. Step (c) : lnX_pipe_direct_tx_transfer_en_o is driven high by the R-Tile Avalon Streaming IP indicating the EMIB bridge between the R-Tile Avalon Streaming IP and the FPGA fabric is ready.
  4. Step (d) : lnX_pipe_direct_pld_pcs_rst_n_i is driven high by the Soft IP controller. The Soft IP controller must also drive high the per-lane lnX_pipe_direct_pld_pcs_rst_n_i signal to come out of reset after the per-lane lnX_pipe_direct_tx_transfer_en_o signal is driven high.
  5. Step (e) : pipe_direct_pld_tx_clk_out_o becomes active as the TX clock output to be used by the Soft IP controller for the TX path.
  6. Step (f) : lnX_pipe_direct_phystatus_o is driven low by the R-Tile Avalon Streaming IP indicating a reset exit.
  7. Step (g) : lnX_pipe_direct_phystatus_o is pulsed and in
  8. Step (h) : lnX_pipe_direct_rx_status_o is pulsed as well. Both pulses confirm to the Soft IP controller the RX detection.
  9. Step (j) : The Soft IP controller starts sending data on the lnX_pipe_direct_txdata_i bus along with its corresponding lnX_pipe_direct_txdatavalid0_i at Step (k) and lnX_pipe_direct_txdatavalid1_i signals at Step (l). Refer to PIPE Direct TX Datapath for additional details.
For the RX path:
  1. Step (m) : After TX data is transmitted from the Soft IP controller and once enough RX data has been received from the link partner to recover the clock, the lnX_pipe_direct_cdrlockstatus_o signal is driven high.
  2. Step (n) : The lnX_pipe_direct_cdrlock2data_o signal is driven high indicating the CDR has locked to the data being received.
  3. Step (o) : The lnX_pipe_direct_rx_clk_out_o signal becomes active as the RX clock output to be used by the Soft IP controller for the RX data path.
  4. Step (p) : The ln_pipe_direct_reset_status_n_o signal is driven high by the R-Tile Avalon Streaming IP indicating the RX data path is out of reset.
  5. Step (q) : The Soft IP controller starts sampling data on the lnX_pipe_direct_rxdata_o while qualifying the data with its corresponding lnX_pipe_direct_rxdatavalid0_i and lnX_pipe_direct_rxdatavalid1_i signals. Application logic needs to wait for the assertion of the corresponding lane's ln_pipe_direct_reset_status_n_o[15:0] to sample the Rx data. Refer to PIPE Direct RX Datapath for additional details.

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