R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 3/28/2022
Public

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3.2.1. SR-IOV Support

The R-tile IP for PCIe supports SR-IOV. The endpoint port controllers in the IP support up to eight physical functions (PF) and 2048 virtual functions (VF) per SR-IOV endpoint. The RP port controllers in the IP do not support SR-IOV, and only support one PF.

Note: Ports 0 and 1 can support eight PFs and 2048 VFs. Ports 2 and 3 do not support SR-IOV, and only support one PF.

The VF configuration space registers are hardened in the R-tile. The specific VF-based work queues and interrupt tables must be implemented in the FPGA fabric by the user application.

For more details on the configuration space registers required for virtualization support, refer to R-Tile Configuration Register Maps.

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