R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 3/28/2022
Public

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4.4.8.2.2. D3Hot Exit Initiated by EP

For the Endpoint to exit the D3hot state, the PME_en bit in the Power Management Control and Status register needs to be set first by the Host (prior to the D3hot entry). The Application Layer can then request a wake-up event by asserting apps_pm_xmt_pme_i, which causes the IP core to transmit a PM_PME message. In addition, the IP core sets the PME_status bit in the Power Management Control and Status register to notify software that it has requested the D3hot exit transition.

Figure 34. Timing Diagram for D3Hot Exit Initiated by EP

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