R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 3/28/2022
Public

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4.4.1.5. Tag Allocation

For the x16 Controller (Port 0), the R-Tile Avalon Streaming Hard IP supports the 10-bit tag Requester capability. It supports up to 768 outstanding Non-Posted Requests (NPRs) with valid tag values ranging from 256 to 1023.

For the x8 (Port 1) and x4 Controllers (Port 2/3) the Hard IP supports the 10-bit tag Requester capability. They support up to 512 outstanding Non-Posted Requests (NPRs) with valid tag values ranging from 256 to 768.

When enabling both 10-bit tags and 8-bit tags, the LSB 8 bits of the 8-bit tags cannot be shared with the LSB 8 bits of the 10-bit tags.

Note that all PFs and their associated VFs share the same tag space. This means that different PFs and VFs cannot have outstanding tags having the same tag values.

In the TLP bypass mode, there is no restriction on the tag allocation since the R-Tile PCIe Hard IP does not do any tag management. Hence, 10-bit tags can be used without any restriction across all the cores.

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