R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide
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2.4. PIPE Direct Mode
In PIPE Direct mode, application logic is responsible for implementing the Transaction Layer, Data Link Layer and the MAC (including the 8b/10b, 128b/130b Encoder/Decoder, Elastic Buffer, etc.) in your application logic in the FPGA fabric. Only the PHY layer inside the R-tile IP for PCIe is active as shown in the following figure.