R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 3/28/2022
Public

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4.4.1.3. Avalon® Streaming RX Interface

The Application Layer receives data from the Transaction Layer of the R-tile PCI Express IP core over the Avalon® Streaming RX interface. The application must assert rx_st_ready_i before transfers can begin. For R-tile, the rx_st_ready_i has to be always high. The buffer control in user logic needs to be handled by the RX Flow Control interface. Refer to RX Flow Control Interface for more details.

This interface supports four rx_st_sop_o signals and four rx_st_eop_o signals per cycle when the R-tile IP is operating in a 1x16 configuration. It also does not follow a fixed latency between rx_st_ready_i and rx_st_valid_o as specified by the Avalon® Interface Specifications.

The x16 core provides four segments with each one having 256 bits of data (rx_st_data_o[255:0]), 128 bits of header (rx_st_hdr_o[127:0]), and 32 bits of TLP prefix (rx_st_ prfx_o[31:0]). If this core is configured in the 1x16 mode, four segments are used, so the data bus becomes a 1024-bit bus with four rx_st_data_o[255:0]. The start of packet can appear in any of the segments, as indicated by the rx_st_sop_o signal in each segment.

Note:
In the case where the Hard IP receives multiple SOPs, there will be only 2 SOPs observed on a single clock cycle on the Avalon Streaming RX interface with the following combinations possible:
  • rx_stN_sop_i pulses on segments 0 and 2 (st0 and st2), or
  • rx_stN_sop_i pulses on segments 1 and 3 (st1 and st3).

For multiple TLPs arriving on the same clock cycle, the application logic needs to process the TLPs in the order of the segment index (i.e. segment st0->st1->st2->st3->st0). For a single TLP spanning across multiple segments, the application logic also needs to process the TLP in the order of the segment index (segment st0->st1->st2->st3->st0)

If this core is configured in the 2x8 mode, there are still four Avalon® Streaming segments (two for each x8 port) if the core IP is set up in double-width mode.

Parity generation is done via a 32:1 XOR (i.e. there is one parity bit for every 32 data, header or prefix bits).

Table 54.  Avalon Streaming RX Interface Signals
Signal Name Direction Description EP/RP/BP Clock Domain
pX_rx_stN_data_o[W:0] where

X = 0,1,2,3 (IP core number) and W varies based on the core.

N = 0,1,2,3 (segment number)

Output This is the Receive data bus. The Application Layer receives data from the Transaction Layer of the IP core on this bus. EP/RP/BP coreclkout_hip
pX_rx_stN_hdr_o[127:0] where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output This is the received header, which follows the TLP header format of the PCIe specifications. EP/RP/BP coreclkout_hip
pX_rx_stN_prefix_o[31:0] where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output

This is the first TLP prefix received, which follows the TLP prefix format of the PCIe specifications. PASID is supported.

These signals are valid when the corresponding rx_st_sop_o is asserted.

The TLP prefix uses a Big Endian implementation (i.e, the Fmt field is in bits [31:29] and the Type field is in bits [28:24]).

If no prefix is present for a given TLP, that dword (including the Fmt field) is all zeros.

EP/RP/BP coreclkout_hip
pX_rx_stN_sop_o where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output

Signals the first cycle of the TLP when asserted in conjunction with the corresponding bit of rx_stN_valid_o.

rx_stN_sop_o: When asserted, signals the start of a TLP on rx_stN_data_o[255:0].

For example, when asserted, rx_st2_sop_o signals the start of a TLP on rx_st2_data_o[255:0].

EP/RP/BP coreclkout_hip
pX_rx_stN_eop_o where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output

Signals the last cycle of the TLP when asserted in conjunction with the corresponding bit of rx_stN_valid_o.

rx_stN_eop_o: When asserted, signals the end of a TLP on rx_stN_data_o[255:0].

For example, when asserted, rx_st2_eop_o signals the end of a TLP on rx_st2_data_o[255:0].

EP/RP/BP coreclkout_hip
pX_rx_stN_dvalid_o where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output These signals qualify the rx_stN_data_o signals going into the Application Layer. EP/RP/BP coreclkout_hip
pX_rx_stN_hvalid_o where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output These signals qualify the rx_stN_hdr_o signals going into the Application Layer. EP/RP/BP coreclkout_hip
pX_rx_stN_pvalid_o where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output These signals qualify the rx_stN_prefix_o signals going into the Application Layer. EP/RP/BP coreclkout_hip
pX_rx_stN_data_par_o[Z:0] where

X = 0,1,2,3 (IP core number) and Z varies based on the core.

N = 0,1,2,3 (segment number)

Output Parity signals for rx_stN_data_o. EP/RP/BP coreclkout_hip
pX_rx_stN_hdr_par_o[3:0] where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output Parity signals for rx_stN_hdr_o. EP/RP/BP coreclkout_hip
pX_rx_stN_prefix_par_o where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output Parity signals for rx_stN_prefix_o. EP/RP/BP coreclkout_hip
pX_rx_st_ready_i Input Indicates the Application Layer is ready to accept data. This signal should always be set to 1. The Flow Control on the RX side is handled through the Credit Control Interface. EP/RP/BP coreclkout_hip
pX_rx_stN_empty_o[2:0] where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output

Specifies the number of dwords that are empty during cycles when the rx_stN_eop_o signals are asserted. These signals are not valid when the rx_stN_eop_o signals are not asserted.

EP/RP/BP coreclkout_hip
pX_rx_stN_bar_o[2:0] where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output

Specify the BAR for the TLP being output.

These outputs are valid when both rx_stN_sop_o and rx_stN_valid_o are asserted.

EP/RP coreclkout_hip
pX_rx_stN_vfactive_o where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output

When asserted, these signals indicate that the received TLP is targeting a virtual function. When these signals are deasserted, the received TLP is targeting a physical function and the rx_stN_pfnum_o signals indicate the function number.

These signals are valid when the corresponding rx_stN_sop_o is asserted.

EP/RP coreclkout_hip
pX_rx_stN_vfnum_o[10:0] where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output

Specify the target VF number for the received TLP. The application uses this information for both request and completion TLPs. For a completion TLP, these bits specify the VF number of the requester for this completion TLP.

These signals are valid when rx_stN_vf_active_o and the corresponding rx_stN_sop_o are asserted.

EP/RP coreclkout_hip
pX_rx_stN_pfnum_o[2:0] where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output

Specify the target physical function number for the received TLP.

These signals are valid when the corresponding rx_stN_sop_o is asserted.

EP/RP coreclkout_hip
As an example, Avalon® Streaming RX Interface Timings below shows the behavior of the Avalon Streaming RX interface with multiple TLPs, and each of those TLPs spanning across multiple segments. The following text describes the waveforms per clock cycle:
  1. Clock cycle 1: Application logic asserts p0_rx_st_ready_i signal. This signal must be set high all the time. The RX flow control must be handled by the Application logic using the RX Flow Control interface (refer to RX Flow Control Interface for details).
  2. Clock cycle 2:
    1. The start of the first TLP (T0) arrives in segment 1, when p0_rx_st1_sop_o is asserted.
    2. The signal p0_rx_st1_hvalid_o is asserted to validate the header of this first TLP (T0H0) in the p0_rx_st1_hdr_o bus.
    3. The signal p0_rx_st1_dvalid_o is asserted to validate the data of this first TLP (T0D0) in the p0_rx_st1_data_o bus.
    4. The end of this first TLP (T0) is in segment 2, denoted by the assertion of p0_rx_st2_eop_o.
    5. The signal p0_rx_st2_dvalid_o is asserted to validate the data of this first TLP (T0D1) in the p0_rx_st2_data_o bus.
    6. The bus p0_rx_st2_empty_o indicates the number of dwords that are not valid in the p0_rx_st2_data_o bus (T0D1).
  3. Clock cycle 3:
    1. The next TLP (T1), arrives in segment 1, as denoted by the assertion of p0_rx_st1_sop_o.
    2. The signal p0_rx_st1_hvalid_o is asserted to validate the header of this TLP (T1H0) in the p0_rx_st1_hdr_o bus.
    3. The signal p0_rx_st1_dvalid_o is asserted to validate the data of this TLP (T1D0) in the p0_rx_st1_data_o bus.
    4. The signal p0_rx_st2_dvalid_o is asserted to validate the data of this TLP (T1D1) in the p0_rx_st2_data_o bus.
    5. The signal p0_rx_st3_dvalid_o is asserted to validate the data of this TLP (T1D2) in the p0_rx_st3_data_o bus.
  4. Clock cycle 4:
    1. The end of the T1 TLP is in segment 0, denoted by the assertion of p0_rx_st0_eop_o.
    2. The signal p0_rx_st0_dvalid_o is asserted to validate the data of this TLP (T1D3) in the p0_rx_st0_data_o bus.
    3. The bus p0_rx_st0_empty_o indicates the number of dwords that are not valid in the p0_rx_st0_data_o bus (T1D3).

The next TLP arrives in the next clock cycle in segment 1 and finishes in segment 0.

Figure 26.  Avalon® Streaming RX Interface Timings

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