R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4.8.4. D3Cold Exit

When configured as an endpoint, the R-Tile Avalon® Streaming IP cannot initiate a transition from D3Cold to D0. Depending on the Link state, the exit transition must be as follows:

From L2:

The system host will attempt to send a CfgWr to the Power Management Control register to go to D0. This will automatically first cause a transition from L2 to L0 started by the host. Then, the CfgWr will be sent to the Power Management Control register in the R-Tile IP to change the power state and pme enable.

From L3:

A cold reset is required to perform a complete FPGA configuration and transition the link to L0.

When the IP is configured as a Root Port, a cold reset is required to perform a complete FPGA configuration and transition the link from L2 or L3 back to L0.

Did you find the information on this page useful?

Characters remaining:

Feedback Message