R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.2.2.5.22. VirtIO PCI Configuration Access Data Register (Address: 0x03B)

The PCI configuration data register indicates the data for BAR access.

Table 40.  VirtIO PCI Configuration Access Data Register
Bit Location Description Access Type Default Value
31:0 PCI Configuration Data RW Undefined

Did you find the information on this page useful?

Characters remaining:

Feedback Message