R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 3/28/2022
Public

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4.4.8.3. D3Cold Entry

The following sequence describes the D3Cold entry procedure. All transmissions on the Avalon Streaming TX and RX interfaces must have completed before the R-Tile PCIe IP core can begin the L1 request (Enter_L1 DLLP). In addition, the RX buffer must be empty and the app_xfer_pending_i signal must be deasserted.

  1. Software on the host side writes the Power Management Control register to request the entry to D3Hot state.
  2. The endpoint stops transmitting requests when it has been taken out of D0. Application logic can use the pm_dstate_o signal to monitor the current D state.
  3. The link transitions to L1. Application logic can use the pm_curnt_state_o signal to monitor the current L state.
  4. Software on the host side sends the PME_Turn_Off Message to the endpoint to initiate a power down. The delivery of the message TLP causes the link to transition to L0 and the message will also be passed on to the Avalon Streaming RX interface.
  5. The R-Tile IP core automatically transmits a PME_TO_Ack Message to acknowledge the Turn Off request.
  6. When ready for the power removal D3Cold state, the application logic in the Endpoint asserts p#_app_ready_entr_l23_i. The R-Tile IP core will then send the PM_Enter_L23 DLLP and initiate the Link transition to L2/L3 Ready.
  7. In this state, power can be removed to transition the link to L3. Alternatively, if supported by the Host system, the link can be transitioned to L2 while maintaining refclk and Vaux.

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