R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 3/28/2022
Public

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Document Table of Contents

4.1. Overview

There are four PCIe cores in R-tile. You can determine which core each interface in this section belongs to by looking at the prefixes in the signal names:
  • p0 : x16 core
  • p1 : x8 core
  • p2 : x4_0 core
  • p3 : x4_1 core
Note: The x4_0 core is only available in devices with the suffix R2 or R3 in their OPN number. For additional details on OPN decoding, refer to the Intel® Agilex™ FPGAs and SoCs Device Overview.

R-tile Top-Level Block Diagram in PCI Express Mode below shows the top-level signals of this IP. Note that the signal names in the figure will get the appropriate prefixes pn (where n = 0, 1, 2 or 3) depending on which of the supported topologies (x16, x8x8, x4x4x4x4) the R-tile Avalon® streaming IP for PCIe is in.

The only cases where the interface signal names do not get the pn prefixes are the interfaces that are common for all the cores, like clocks and resets.

Each of the cores has its own Avalon® streaming interface to the user logic in the FPGA fabric. The number of IP-to-User Logic interfaces exposed to the FPGA fabric are different based on the topologies:
Table 45.  IP to FPGA Fabric Interfaces Summary
Topology Avalon-ST Interface Count Data Width (each Interface) Header Width (each Interface) TLP Prefix Width (each Interface) Application Clock Frequency Note
Gen5 1x16 EP/RP/BP 1 1024-bit (four 256-bit segments) 512-bit (four 128-bit segments) 128-bit (four 32-bit segments)

400 MHz / 425 MHz / 450 MHz / 475 MHz / 500 MHz

 
Gen4 1x16 EP/RP/BP 1 1024-bit (four 256-bit segments) 512-bit (four 128-bit segments) 128-bit (four 32-bit segments)

250 MHz / 275 MHz / 300 MHz

 
512-bit (two 256-bit segments) 256-bit (two 128-bit segments) 64-bit (two 32-bit segments)

400 MHz / 425 MHz / 450 MHz / 475 MHz / 500 MHz

Gen3 1x16 EP/RP/BP 1 1024-bit (four 256-bit segments) 512-bit (four 128-bit segments) 128-bit (four 32-bit segments)

250 MHz / 275 MHz / 300 MHz

 
512-bit (two 256-bit segments) 256-bit (two 128-bit segments) 64-bit (two 32-bit segments)

400 MHz / 425 MHz / 450 MHz / 475 MHz / 500 MHz

3
Gen5 2x8 EP/RP/BP 2 512-bit (two 256-bit segments) 256-bit (two 128-bit segments) 64-bit (two 32-bit segments)

400 MHz / 425 MHz / 450 MHz / 475 MHz / 500 MHz

 
Gen4 2x8 EP/RP/BP 2 512-bit (two 256-bit segments) 256-bit (two 128-bit segments) 64-bit (two 32-bit segments)

250 MHz / 275 MHz / 300 MHz

 
256-bit (one 256-bit segment) 128-bit (one 128-bit segment) 32-bit (one 32-bit segment)

400 MHz / 425 MHz / 450 MHz / 475 MHz / 500 MHz

3
Gen3 2x8 EP/RP/BP 2 512-bit (two 256-bit segments) 256-bit (two 128-bit segments) 64-bit (two 32-bit segments)

250 MHz / 275 MHz / 300 MHz

 
256-bit (one 256-bit segment) 128-bit (one 128-bit segment) 32-bit (one 32-bit segment)

250 MHz / 275 MHz / 300 MHz

3
Gen5 4x4 EP/RP/BP 4 256-bit (two 128-bit segments) 256-bit (two 128-bit segments) 64-bit (two 32-bit segments)

400 MHz / 425 MHz / 450 MHz / 475 MHz / 500 MHz

 
Gen4 4x4 EP/RP/BP 4 256-bit (two 128-bit segments) 256-bit (two 128-bit segments) 64-bit (two 32-bit segments)

400 MHz / 425 MHz / 450 MHz / 475 MHz / 500 MHz

 
128-bit (one 128-bit segment) 128-bit (one 128-bit segment) 32-bit (one 32-bit segment)

400 MHz / 425 MHz / 450 MHz / 475 MHz / 500 MHz

3
Gen3 4x4 EP/RP/BP 4 256-bit (two 128-bit segments) 256-bit (two 128-bit segments) 64-bit (two 32-bit segments)

250 MHz / 275 MHz / 300 MHz

 
128-bit (one 128-bit segment) 128-bit (one 128-bit segment) 32-bit (one 32-bit segment)

250 MHz / 275 MHz / 300 MHz

3
Figure 19. R-tile Top-Level Block Diagram in PCI Express Mode
Note:

pX: X is port number, ranges from 0 to 3.

st#: # is segment number, ranges from 0 to 3.

3 This topology is only available in devices with the suffix R2 or R3 in their OPN number. For more details on OPN decoding, refer to the Intel® Agilex™ FPGAs and SoCs Device Overview.

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