R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 3/28/2022

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4.4. PCI Express Mode

In PCI Express mode, only the PCI Express controller stack is active. The four PCI Express cores (x16, x8, x4_0 and x4_1) interface with the application logic in the FPGA fabric via Avalon® streaming interfaces.

Figure 20. R-tile Top-Level Block Diagram in PCI Express Mode

pX: X is port number, ranges from 0 to 3.

st#: # is segment number, ranges from 0 to 3.

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