R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 3/28/2022
Public

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Document Table of Contents

1.2. Features

The R-tile Avalon® streaming IP for PCI Express* supports the following features:

  • Includes a complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as a Hard IP.
  • Supports Root Port (RP), Endpoint (EP) and TLP Bypass (BP) modes.
    Table 1.  Configurations Natively Supported by R-tileEndpoint = EP; Root Port = RP; TLP Bypass = BP
    Configuration Application Interface Data Width (bits) EP/RP/BP
    Gen5/Gen4/Gen3 x16 1024 EP/RP/BP
    Gen4/Gen3 x16 512 1 EP/RP/BP
    Gen5/Gen4/Gen3 x8x8 512 EP/RP/BP
    Gen4/Gen3 x8x8 256 1 EP/RP/BP
    Gen5/Gen4/Gen3 x4x4x4x4 256 EP/RP/BP
    Gen4/Gen3 x4x4x4x4 128 1 EP/RP/BP
    PIPE Direct 64 bits per Lane N/A
    Note: Gen1/Gen2 configurations are supported via link down-training.
  • Table 2.  Topologies Supported by R-tile
    Topology\ Lane# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
    x16 Port 0 (EP/RP/BP)
    x8x8 Port 0 (EP/RP/BP) Port 1 (EP/RP/BP)
    x4x4x4x4 Port 2 (EP/RP/BP) Port 0 (EP/RP/BP) Port 1 (EP/RP/BP) Port 3 (EP/RP/BP)
    PIPE Direct PIPE Direct
    Note: Port 2 is only available in devices with the suffix R2 or R3 in their OPN number. For additional details on OPN decoding, refer to Intel® Agilex™ FPGAs and SoCs Device Overview.
  • The following PIPE Direct bundle modes are supported and are selectable via the PIPE Direct Mode menu in the Parameter Editor in Intel® Quartus® Prime:
    • 1x16
    • 2x8
    • 4x4
    • 8x2
    • 16x1
    • 2x4 : 1x8
    • 4x2 : 1x8
    • 8x1 : 1x8
    • 1x8 : 2x4
    • 4x2 : 2x4
    • 8x1 : 2x4
    • 1x8 : 4x2
    • 2x4 : 4x2
    • 8x1 : 4x2
    • 1x8 : 8x1
    • 2x4 : 8x1
    • 4x2 : 8x1
    Note: 1x16 means all 16 PIPE Direct channels act in a bundle mode. 16x1 means all 16 channels act as independent channels. 2x8 means the channels are in two 8-channel bundles. 2x4 : 1x8 means the channels in the Lower 8 lanes are organized as two 4-channel bundles, while the channels in the Upper 8 lanes are in an 8-channel bundle.
  • Static port bifurcation (x8x8, x4x4x4).
  • Supports Precision Time Management (PTM) (Endpoint only).
    Note: Only Ports 0 and 1 support PTM.
  • Supports TLP Bypass mode in Upstream or Downstream configuration.
    • Supports one x16, two x8, or four x4 interfaces.
  • Supports up to 512-byte maximum payload size (MPS).
  • Supports up to 4096-byte (4 KB) maximum read request size (MRRS).
  • Single Virtual Channel (VC).
  • Latency Tolerance Reporting (LTR).
  • Page Request Services (PRS).
    Note: Only Ports 0 and 1 support PRS.
  • Completion Timeout Ranges.
  • Atomic Operations (FetchAdd/Swap/CAS).
  • Extended Tag Support.
    • 10-bit Tag Support (Maximum of 768 outstanding tags (x16) / 512 outstanding tags (x8/x4) at any given time, for all functions combined).
  • Separate Refclk with Independent Spread Spectrum Clocking (SRIS).
  • Separate Refclk with no Spread Spectrum Clocking (SRNS).
  • Common Refclk architecture.
  • PCI Express* Advanced Error Reporting (PF only).
    Note: Advanced Error Reporting is always enabled in the R-tile Avalon® streaming IP for PCIe.
  • ECRC generation and checking (when the IP is not in TLP Bypass mode).
    • Application logic needs to handle ECRC generation and checking when the IP is in TLP Bypass mode.
  • Data bus parity protection.
  • Supports D0 and D3 Hot PCIe power states.
  • Supports L1 Active State Power Management (ASPM).
  • Lane Margining at Receiver.
  • Retimers presence detection.
Multifunction and Virtualization Features:
  • SR-IOV support (Port 0 and Port 1 only).
    Note: Ports 0 and 1 can support 8 PFs and 2K VFs. Ports 2 and 3 do not support SR-IOV, and only support 1 PF.
  • Access Control Service (ACS) capability.
    Note: For ACS, only ports 0 and 1 are supported.
  • Alternative Routing-ID Interpretation (ARI).
  • Function Level Reset (FLR).
    Note: Only Ports 0 and 1 support FLR.
  • TLP Processing Hint (TPH).
    Note: TPH supports the "No Steering Tag (ST)" mode only.
  • Address Translation Services (ATS).
  • Process Address Space ID (PasID).
    Note: Scalable IO and Shared Virtual Memory (SVM) may be available in a future Intel® Quartus® Prime release.
  • Configuration Intercept Interface (CII).
  • Soft VirtIO support.
    Note: VirtIO support for Ports 2 and 3 is only available in devices with the suffix R2 or R3 in their OPN number. For additional details on OPN decoding, refer to Intel® Agilex™ FPGAs and SoCs Device Overview.
IP Features:
  • User packet interface with separate header, data and prefix.
  • User packet interface with a split-bus architecture where the header, data and prefix busses consist of four segments each (x16 mode only). This improves the bandwidth efficiency of this interface as it can handle up to four TLPs in any given cycle.
  • Up to 768 outstanding Non-Posted requests (x16 core only).
  • Up to 512 outstanding Non-Posted requests (x8 and x4 cores).
  • Summary of outstanding Non-Posted requests supported when 8-bit tags or 10-bit tags are enabled:
    Table 3.  Outstanding Non-Posted Requests Supported
    Ports Active Cores 8-bit Tags 10-bit Tags
    0 x16 256 768 (*)
    1 x8 256 512
    2 and 3 x4 256 512
    Note: (*): Use tags 256 to 1023.
  • Completion timeout interface.
    • The PCIe Hard IP can optionally track outgoing non-posted packets to report completion timeout information to the application.
  • You cannot change the pin allocations for the R-tile Avalon® streaming IP for PCI Express* in the Intel® Quartus® Prime project. However, this IP does support lane reversal and polarity inversion on the PCB by default.
  • Supports Autonomous Hard IP mode.
    • This mode allows the PCIe Hard IP to communicate with the Host before the FPGA configuration and entry into User mode are complete.
      Note: Unless Readiness Notifications mechanisms are used, the Root Complex and/or system software must allow at least 1 second after a Conventional Reset of a device before it may determine that a device that fails to return a Successful Completion status for a valid Configuration Request is a broken device. This period is independent of how quickly Link training completes.
  • Supports CvP Init and CvP Update.
    Note: For Gen3, Gen4 and Gen5 x16 variants, Port 0 (corresponding to lanes 0 - 15) supports the CvP features. For Gen3, Gen4 and Gen5 x8 variants, only Port 0 (corresponding to lanes 0 - 7) supports the CvP features. Port 1 (corresponding to lanes 8 - 15) does not support CvP.
  • VCS*, VCS* MX, and Siemens EDA QuestaSim* are the only simulators supported in the 22.1 release of Intel® Quartus® Prime.
  • The R-tile PHY layer does not support sending a Beacon signal.
Note: Throughout this User Guide, the term Avalon-ST may be used as an abbreviation for the Avalon® streaming interface or IP.
1 These configurations are only available in devices with the suffix R2 or R3 in their OPN number. For more details on OPN decoding, refer to Intel® Agilex™ FPGAs and SoCs Device Overview

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