Visible to Intel only — GUID: reference_TCL_tcl_pkg_sdc_ver_1_5_cmd_reset_design
Ixiasoft
Visible to Intel only — GUID: reference_TCL_tcl_pkg_sdc_ver_1_5_cmd_reset_design
Ixiasoft
3.1.27.19. reset_design (::quartus::sdc)
The following table displays information for the reset_design Tcl command:
Tcl Package and Version | Belongs to ::quartus::sdc |
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Syntax | reset_design [-h | -help] [-long_help] | ||
Arguments | -h | -help | Short help | |
-long_help | Long help with examples and possible return values | ||
Description | Removes all assignments from the design. This includes clocks, generated clocks, derived clocks, input delays, output delays, clock latency, clock uncertainty, clock groups, false paths, multicycle paths, min delays, and max delays. After reset_design is called, the design should be in the same state as it would be if create_timing_netlist was just called. |
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Example Usage | |
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Return Value | Code Name | Code | String Return |
TCL_OK | 0 | INFO: Operation successful | |
TCL_ERROR | 1 | ERROR: Timing netlist does not exist. Use create_timing_netlist to create a timing netlist. |