Intel® Quartus® Prime Pro Edition User Guide: Scripting

ID 683432
Date 10/04/2021

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Document Table of Contents
Give Feedback create_timing_netlist (::quartus::sta)

The following table displays information for the create_timing_netlist Tcl command:

Tcl Package and Version

Belongs to ::quartus::sta

Syntax create_timing_netlist [-h | -help] [-long_help] [-force_dat] [-grade <c|i|m|e|a> ] [-model <fast|slow> ] [-no_latch] [-post_map] [-post_syn] [-snapshot <snapshot> ] [-speed <speed> ] [-temperature <value_in_C> ] [-voltage <value_in_mV> ] [-zero_ic_delays] [ <operating_conditions> ]
Arguments -h | -help Short help
-long_help Long help with examples and possible return values
-force_dat Option to force delay annotation
-grade <c|i|m|e|a> Option to specify temperature grade
-model <fast|slow> Option to specify timing model
-no_latch Option to disable the analysis of latches as synchronous elements
-post_map Option to perform timing analysis on the post-synthesis netlist
-post_syn Option to perform timing analysis on the post-synthesis netlist
-snapshot <snapshot> Snapshot of the design to load
-speed <speed> Speed grade
-temperature <value_in_C> Operating temperature
-voltage <value_in_mV> Operating voltage
-zero_ic_delays Option to set all IC delays to zero
<operating_conditions> Operating conditions Tcl object name string

Creates the timing netlist by annotating the atom netlist with delay information using post-fitting results. Use the -post_map option to obtain post-synthesis results. In an incremental compilation flow, after Analysis and Synthesis, merge the partitions in your design using the merge_partitions Tcl command (or the quartus_cdb executable) to complete the creation of a post-synthesis netlist before you use the -post_map option to create a timing netlist. In Quartus Prime Pro edition, you can use the -snapshot option to specify which netlist you want to perform timing analysis on. The create_timing_netlist command skips delay annotation by default.