3.1.29.5. create_timing_netlist (::quartus::sta)

Intel® Quartus® Prime Pro Edition User Guide: Scripting

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ID 683432

Date 10/04/2021

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3.1.29.5. create_timing_netlist (::quartus::sta)

The following table displays information for the create_timing_netlist Tcl command:

Tcl Package and Version	Belongs to ::quartus::sta
Syntax	`create_timing_netlist [-h \| -help] [-long_help]` `[-force_dat]` `[-grade` <c\|i\|m\|e\|a> `]` `[-model` <fast\|slow> `]` `[-no_latch]` `[-post_map]` `[-post_syn]` `[-snapshot` <snapshot> `]` `[-speed` <speed> `]` `[-temperature` <value_in_C> `]` `[-voltage` <value_in_mV> `]` `[-zero_ic_delays]` `[` <operating_conditions> `]`
Arguments	`-h \| -help`		Short help
	`-long_help`		Long help with examples and possible return values
	`-force_dat`		Option to force delay annotation
	`-grade` <c\|i\|m\|e\|a>		Option to specify temperature grade
	`-model` <fast\|slow>		Option to specify timing model
	`-no_latch`		Option to disable the analysis of latches as synchronous elements
	`-post_map`		Option to perform timing analysis on the post-synthesis netlist
	`-post_syn`		Option to perform timing analysis on the post-synthesis netlist
	`-snapshot` <snapshot>		Snapshot of the design to load
	`-speed` <speed>		Speed grade
	`-temperature` <value_in_C>		Operating temperature
	`-voltage` <value_in_mV>		Operating voltage
	`-zero_ic_delays`		Option to set all IC delays to zero
	<operating_conditions>		Operating conditions Tcl object name string
Description	Creates the timing netlist by annotating the atom netlist with delay information using post-fitting results. Use the -post_map option to obtain post-synthesis results. In an incremental compilation flow, after Analysis and Synthesis, merge the partitions in your design using the merge_partitions Tcl command (or the quartus_cdb executable) to complete the creation of a post-synthesis netlist before you use the -post_map option to create a timing netlist. In Quartus Prime Pro edition, you can use the -snapshot option to specify which netlist you want to perform timing analysis on. The create_timing_netlist command skips delay annotation by default. Use -force_dat to rerun delay annotation. This is required if any delay annotation setting is changed in the Quartus Prime project revision (e.g. OUTPUT_PIN_LOAD). Use "-model fast" to run the analysis using the fast corner delay models first. The -temperature, -voltage, and -speed, options are also available. See help for set_operating_conditions for details on these options. You can use model, temperature and voltage options to specify operating conditions while creating timing netlist (temperature and voltage options are not supported by all families). You can also set operating conditions by passing an operating conditions object name as a positional argument to create_timing_netlist command. After the timing netlist has been created, you can use set_operating_conditions command to change timing models without deleting and re-creating the timing netlist. Use the -grade option to analyze the design at a different temperature grade. This option is provided to support what-if analysis and is not recommended for final sign-off analysis. Use the -no_latch option to analyze latches as combinational loops instead of synchronous elements. Use the -zero_ic_delays option to set all IC delays in the netlist to zero.
Example Usage	project_open my_top # Create timing netlist before calling # any report functions create_timing_netlist # Read SDC and update timing read_sdc update_timing_netlist # Ready to call report functions report_timing -npaths 1 -clock_setup # The following command is optional delete_timing_netlist project_close project_open my_top # Report worst case period for -9 speed grade create_timing_netlist -speed 9 # Read SDC and update timing read_sdc update_timing_netlist report_timing -clock_setup -clock_filter clk delete_timing_netlist # Report hold violation for fastest corner # Use set_operating_conditions instead create_timing_netlist -model fast # Read SDC and update timing read_sdc update_timing_netlist report_timing -clock_hold -clock_filter clk delete_timing_netlist # If Delay Annotation has been run for the fast corner # Force Delay Annotation create_timing_netlist -model fast -force_dat # Read SDC and update timing read_sdc update_timing_netlist report_timing -clock_hold -clock_filter clk delete_timing_netlist # Report worst case period for post-technology mapping netlist create_timing_netlist -post_map # Read SDC and update timing read_sdc update_timing_netlist report_timing -clock_setup -clock_filter clk delete_timing_netlist project_close
Return Value	Code Name	Code	String Return
	TCL_OK	0	INFO: Operation successful
	TCL_ERROR	1	ERROR: The TCL command <string> is not supported in quartus_fit. It is only supported in quartus_sta. Please use quartus_sta instead of quartus_fit if you want to use this TCL command.
	TCL_ERROR	1	ERROR: Can't create timing netlist for device family <string>. Run Analysis and Synthesis (quartus_syn) using this device family as a value for the --family option before running the Timing Analyzer (create_timing_netlist).
	TCL_ERROR	1	ERROR: The Fast Forward snapshot cannot be used for sign-off timing analysis. Please see the Fast Forward Timing Closure Recommendations report for performance estimates.
	TCL_ERROR	1	ERROR: Can't run the Timing Analyzer (quartus_sta) -- Periphery placement (quartus_fit --plan) failed or was not run. Run I/O Assignment Analysis (quartus_fit --plan) successfully before running the Timing Analyzer (create_timing_netlist -post_map).
	TCL_ERROR	1	ERROR: Invalid snapshot <string>. Available snapshot(s): <string>
	TCL_ERROR	1	ERROR: Both the -temperature and -voltage options and their values are required.
	TCL_ERROR	1	ERROR: Can't find active revision. Make sure there is an open, active revision name.
	TCL_ERROR	1	ERROR: Could not find the <string> timing netlist on disk. Please run this fitter stage first, and make sure you have enabled Optimize Timing in Advanced Fitter Settings.
	TCL_ERROR	1	ERROR: Option -no_latch is not supported for the current family.
	TCL_ERROR

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