Intel® Quartus® Prime Pro Edition User Guide: Scripting

ID 683432
Date 10/04/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents set_input_delay (::quartus::sdc)

The following table displays information for the set_input_delay Tcl command:

Tcl Package and Version

Belongs to ::quartus::sdc

Syntax set_input_delay [-h | -help] [-long_help] [-add_delay] [-blackbox] -clock <name> [-clock_fall] [-fall] [-max] [-min] [-reference_pin <name> ] [-rise] [-source_latency_included] <delay> <targets>
Arguments -h | -help Short help
-long_help Long help with examples and possible return values
-add_delay Create additional delay constraint instead of overriding previous constraints
-blackbox Create an assignment for a partition boundary port causing it to be treated as a port
-clock <name> Clock name
-clock_fall Specifies that input delay is relative to the falling edge of the clock
-fall Specifies the falling input delay at the port
-max Applies value as maximum data arrival time
-min Applies value as minimum data arrival time
-reference_pin <name> Specifies a pin or port in the design to which the input delay is relative
-rise Specifies the rising input delay at the port
-source_latency_included Specifies that input delay includes added source latency
<delay> Time value
<targets> List of input port type objects

Specifies the data arrival times at the specified input ports relative the clock specified by the -clock option. The clock must refer to a clock name in the design. Input delays can be specified relative to the rising edge (default) or falling edge (-clock_fall) of the clock. Input delays can be specified relative to a pin or a port (-reference_pin) in the clock network. Clock arrival times to the reference pin or port are added to data arrival times. If no -reference_pin is specified, if the input delay is specified relative to a generated clock with a single target, the clock arrival times to the generated clock are added to the data arrival time. If the generated clock has multiple targets, the worst case arrival time to those targets will be used. Input delays can already include clock source latency. By default the clock source latency of the related clock is added to the input delay value, but when the -source_latency_included option is specified, the clock source latency is not added because it was factored into the input delay value. The maximum input dela