Visible to Intel only — GUID: reference_TCL_tcl_pkg_sdc_ext_ver_2_0_cmd_derive_pll_clocks
Ixiasoft
Visible to Intel only — GUID: reference_TCL_tcl_pkg_sdc_ext_ver_2_0_cmd_derive_pll_clocks
Ixiasoft
3.1.28.2. derive_pll_clocks (::quartus::sdc_ext)
The following table displays information for the derive_pll_clocks Tcl command:
Tcl Package and Version | Belongs to ::quartus::sdc_ext |
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Syntax | derive_pll_clocks [-h | -help] [-long_help] [-create_base_clocks] [-use_net_name] | ||
Arguments | -h | -help | Short help | |
-long_help | Long help with examples and possible return values | ||
-create_base_clocks | Creates base clocks on input clock ports of the design that are feeding the PLL | ||
-use_net_name | Use net names as clock names | ||
Description | NOTE: This command is no longer supported for Stratix 10 and later families. Identifies PLLs or similar resources in the design and creates generated clocks for their output clock pins. Multiple generated clocks may be created for each output clock pin if the PLL is using clock switchover, one for the inclk[0] input clock pin and one for the inclk[1] input clock pin. By default this command does not create base clocks on input clock ports that are driving the PLL. When you use the create_base_clocks option, derive_pll_clocks also creates the base clock on an input clock port deriving the PLL. This option does not overwrite an existing clock. By default the clock name is the same as the output clock pin name. To use the net name, use the -use_net_name option. Note that this command is not supported for Stratix 10 and later device families. The only families that still have support for this command are Arria 10 and Cyclone 10GX. The reason why this command has been deprecated is because all PLL clocks are now automatically generated by the SDC files generated alongside the PLL IP. No user action is required. |
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Example Usage | |
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Return Value | Code Name | Code | String Return |
TCL_OK | 0 | INFO: Operation successful | |
TCL_ERROR | 1 | ERROR: Timing netlist does not exist. Use create_timing_netlist to create a timing netlist. |