Intel® Quartus® Prime Pro Edition User Guide: Scripting

ID 683432
Date 10/04/2021
Public

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Document Table of Contents

3.1.24.45. resolve_file_path (::quartus::project)

The following table displays information for the resolve_file_path Tcl command:

Tcl Package and Version

Belongs to ::quartus::project

Syntax resolve_file_path [-h | -help] [-long_help] <file_name>
Arguments -h | -help Short help
-long_help Long help with examples and possible return values
<file_name> Option to specify the file name
Description

Returns the resolved full path of the specified file name. If the file does not exist, the original file name is returned. The Quartus Prime software resolves relative paths by searching for the file in the following directories in the following order: 1) Project directory, which is the directory where the Quartus Prime Settings File (.qsf) is found. 2) Project database directory, which is the "db" directory found under the project directory. 3) Project library directories, which are the directories containing the user-specified libraries that are used only by the current project. 4) User library directories, which are the directories containing the user-specified libraries that are used by all Quartus Prime projects. 5) Quartus Prime library directory, which is the directory containing Quartus Prime libraries.

Example Usage
project_new chiptrip -overwrite

# Set one Verilog source file assignment
set_global_assignment -name VERILOG_FILE chiptrip.v

# Display the resolved full path of the Verilog
# source file assignment
set filename [get_global_assignment -name VERILOG_FILE]
set resolved_fullpath [resolve_file_path $filename]

puts "Full Path: $resolved_fullpath"

# Set more Verilog source file assignments
set_global_assignment -name VERILOG_FILE auto_max.v
set_global_assignment -name VERILOG_FILE speed_ch.v
set_global_assignment -name VERILOG_FILE tick_cnt.v
set_global_assignment -name VERILOG_FILE time_cnt.v

# Display the resolved full path of all the Verilog
# source file assignments
set file_asgns [get_all_global_assignments -name VERILOG_FILE]
foreach_in_collection file_asgn $file_asgns {

    ## Each element in the collection has the following
    ## format: {} {VERILOG_FILE} {<file_name>}

    set filename [lindex $file_asgn 2]
    set resolved_fullpath [resolve_file_path $filename]

    puts "Full Path: $resolved_fullpath"
}

project_close
Return Value Code Name Code String Return
TCL_OK 0 INFO: Operation successful
TCL_ERROR 1 ERROR: Can't find active revision name. Make sure there is an open, active revision name.
TCL_ERROR 1 ERROR: You must open a project before you can use this command.

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