Intel® Quartus® Prime Pro Edition User Guide: Scripting

ID 683432
Date 10/04/2021
Public

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3.1.16.2. generate_ip_file (::quartus::ipgen)

The following table displays information for the generate_ip_file Tcl command:

Tcl Package and Version

Belongs to ::quartus::ipgen

Syntax generate_ip_file [-h | -help] [-long_help] [-clean] [-clear_ip_generation_dirs] [-simulation <verilog|vhdl> ] [-simulator <modelsim|vcs|vcsmx|riviera|xcelium> ] [-synthesis <verilog|vhdl> ] <file>
Arguments -h | -help Short help
-long_help Long help with examples and possible return values
-clean Specify whether pre-existing generation directories should be cleared before generation.
-clear_ip_generation_dirs Specify whether pre-existing generation directories should be cleared before generation.
-simulation <verilog|vhdl> Set the simulation target type. Valid values are verilog or vhdl.
-simulator <modelsim|vcs|vcsmx|riviera|xcelium> Set the simulator target type. Valid values are modelsim, vcs, vcsmx, riviera, and/or xcelium.
-synthesis <verilog|vhdl> Set the synthesis target type. Valid values are verilog or vhdl.
<file> A Platform Designer IP file path. -file="path1;path2"
Description

This command generates the files for a specified Platform Designer IP in the opened project. --synthesis <value>: Specify the synthesis target type. Valid values are verilog or vhdl. This is not a required option. When not specified, it defaults to verilog. --simulation <value>: Specify the simulation target type. Valid values are verilog or vhdl. This is not a required option. When not specified, no simulation files are generated. --simulator <value>: Specify the simulator target type. Valid values are modelsim, vcs, vcsmx, riviera, xcelium. This is not a required option. When not specified, simulation files for all simulators are generated. --clear_ip_generation_dirs: Specify whether pre-existing generation directories should be cleared before generation. This is not a required option. When not specified, the generation directories will not be cleared. --clean: Specify whether pre-existing generation directories should be cleared before generation. This option is a short version of the clear_ip_generation_dirs option. This is not a required option. When not specified, the generation directories will not be cleared.

Example Usage
  # generate the specified Platform Designer IP in the project with the specified targets. Clear any pre-existing 
          # generation directories before performing the generation.
project_open my_project
generate_ip_file my_ip_file.qsys -synthesis verilog -simulation verilog -simulator modelsim -clear_ip_generation_dirs
Return Value Code Name Code String Return
TCL_OK 0 INFO: Operation successful
TCL_ERROR 1 ERROR: The file <string> does not exist in project.
TCL_ERROR 1 ERROR: You must open a project before you can use this command.
TCL_ERROR 1 ERROR: The command failed with an unknown error.

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