Intel® Quartus® Prime Pro Edition User Guide: Scripting

ID 683432
Date 10/04/2021

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Document Table of Contents
Give Feedback report_metastability (::quartus::sta)

The following table displays information for the report_metastability Tcl command:

Tcl Package and Version

Belongs to ::quartus::sta

Syntax report_metastability [-h | -help] [-long_help] [-append] [-file <name> ] [-length <number> ] [-max_length <number> ] [-min_length <number> ] [-nchains <number> ] [-panel_name <name> ] [-stdout]
Arguments -h | -help Short help
-long_help Long help with examples and possible return values
-append If output is sent to a file, this option appends the result to that file. Otherwise, the file will be overwritten. This option is not supported for HTML files.
-file <name> Sends the results to an ASCII or HTML file. Depending on the extension
-length <number> Reports only the synchronizer chains of an exact length
-max_length <number> Specifies the maximum length of a chain that appears in the report (default=no limit)
-min_length <number> Specifies the minimum length of a chain that appears in the report (default=0)
-nchains <number> Specifies the number of chains to report (default=1)
-panel_name <name> Sends the results to the panel and specifies the name of the new panel
-stdout Send output to stdout, via messages. You only need to use this option if you have selected another output format, such as a file, and would also like to receive messages.

Report can be directed to the Tcl console ("-stdout", default), a file ("-file"), the Timing Analyzer graphical interface ("-panel_name"), or any combination of the three. The report_metastability function can be used to estimate the robustness of asynchronous transfers in your design. ---------- Background ---------- Synchronization register chains should be used when transferring data between unrelated clock domains to greatly reduce the probability of the captured data signal becoming metastable. A synchronization register chain is a sequence of registers with the same clock, that is driven by a pin, or logic from an unrelated clock domain. The output of all but the last register in the chain must connect only to the next register, either directly or indirectly through logic. When a register is metastable, its output hovers at a voltage between high and low for a length of time beyond the normal Tco for the register. The design can fail if subsequent registers that use this metastable signal latch different values. Therefore, it is important to properly synchronize data signals to prevent such occurrences. ------ Output ------ The report_metastability function generates a list of synchronization register chains found in the design, and can provide estimates of the Mean Time Between Failures (MTBF) of each chain. The design MTBF is an estimate of the overall robustness of the design, computed from the MTBF results from all synchronization chains with calculated MTBFs. The design MTBF metric is reported only when the design meets timing. Therefore, it is important to fully timing constrain your design. The typical MTBF result assumes typical silicon characteristics for the selected device speed grade, with nominal operating conditions. The worst case MTBF result uses the worst case silicon characteristics for the selected device speed grade, with worst case operating conditions. -------- Settings -------- To get a list of possible synchronization chains, set "Synchronizer Identification" to AUTO in the Timing Analyzer Page in the Settings dialog box. This will set the "Synchronizer Identification" QSF assignment in your QSF file. The Timing Analyzer will use timing constraints to automatically detect synchronization chains in the design. Metastability analysis checks for signal transfers between circuitry in unrelated or asynchronous clock domains, so clock domains must be related correctly with the timing constraints. Set the maximum number of registers to consider as part of one synchronization chain, via the "Synchronization Register Chain Length" setting under Analysis and Synthesis Page in the Settings dialog box. The default length is 2. All the