Arria® 10 or Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide

ID 683425
Date 9/10/2024
Public
Document Table of Contents

2.2. Generating the Testbench

  1. Copy the example design, ep_g3x8_avmm256_integrated.qsys, from the installation directory: <install_dir>/ip/altera/altera_pcie/altera_pcie_a10_ed/example_design/a10/ to your working directory.
  2. Start Platform Designer, by typing the following command:

    qsys-edit

  3. Open ep_g3x8_avmm256_integrated.qsys.
  4. Click Generate > Generate Testbench System.
  5. Specify the following parameters:
    Table 12.  Parameters to Specify in the Generation Dialog Box

    Parameter

    Value

    Testbench System

    Create testbench Platform Designer system

    Standard, BFMs for standard Platform Designer interfaces

    Create testbench simulation model

    Verilog

    Allow mixed-language simulation You can leave this option off.

    Output Directory

    Testbench

    <working_dir>/ep_g3x8_avmm256_integrated_tb
  6. Click Generate.
    Note: Arria® 10 or Cyclone® 10 GX devices do not support the Create timing and resource estimates for third-party EDA synthesis tools option on the Generate > Generate HDL menu. You can select this menu item, but generation fails.